Specifications

3-11
BIOS Setup
Precharge to Active (Trp)
When the DRAM Timing sets to [Manual], the field is adjustable. This item
controls the number of cycles for Row Address Strobe (RAS) to be allowed to
precharge. If insufficient time is allowed for the RAS to accumulate its charge
before DRAM refresh, refreshing may be incomplete and DRAM may fail to
retain data. This item applies only when synchronous DRAM is installed in the
system.
Active to Precharge (Tras)
When the DRAM Timing sets to [Manual], the field is adjustable. This setting
determines the time RAS takes to read from and write to a memory cell.
Active to CMD (Trcd)
When the DRAM Timing sets to [Manual], the field is adjustable. When DRAM
is refreshed, both rows and columns are addressed separately. This setup item
allows you to determine the timing of the transition from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster
the DRAM performance.
REF to ACT/REF (Trfc)
When the DRAM Timing sets to [Manual], the field is adjustable. Auto-refresh
-active to RAS#-active or RAS# auto-refresh.
ACT(0) to ACT(1) (TRRD)
When the DRAM Timing sets to [Manual], the field is adjustable.Specifies the
active-to-active delay of different banks. When DRAM is refreshed, both rows
and columns are addressed separately. This setup item allows you to determine
the timing of the transition from RAS (row address strobe) to CAS (column
address strobe). The less the clock cycles, the faster the DRAM performance.
1T CMD Support
It allows to enable or disable the 1T command rate.
CPU & PCI Bus Control
Press <Enter> to enter the sub-menu:
PCI Master 0 WS Write
When [Enabled], writes to the PCI bus are executed with zero wait states.
PCI Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay trans-
actions cycles. Select [Enabled] to support compliance with PCI specification.
VLink mode selection
This item lets you choose the speed mode between the North Bridge & South
Bridge.