Specifications

CHAPTER 3 AWARD
®
BIOS SETUP
3-14
Bank 0/1 DRAM Timing/Bank 2/3 DRAM Timing/Bank 4/5
DRAM Timing
Set the DRAM latency time to SDRAM 10ns, SDRAM 8ns, Normal,
Medium, Fast and Turbo.
SDRAM Cycle Lenght
The item allows you to select the value for SDRAM Cycle delay
time. The settings are 2ns or 3ns. The default value is 3ns.
DRAM Data Integrity Mode
Select Non-ECC or ECC(error-correcting code), according to the
type of installed DRAM. The settings are Non-ECC (default) or ECC.
DRAM Clock
The default value for this item is Host Clk.
Host Clk DRAM Clock equals to host (system clock)
HCLK-33M DRAM Clock equals to host clock minus 33MHz.
Memory Hole
In order to improve the system’s performance, certain space in
memory can be reserved for ISA cards. This memory must be mapped into
memory space below 16 MB.
Enabled Memory hole supported
Disabled Memory hole not supported
Concurrent PCI Host
Select Enabled allows caching of the system BIOS ROM at F000h-
FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result.
Enabled BIOS access cached
Disabled BIOS access not cached