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8258I N/B Maintenance

5.1 Intel Yonah Processor CPU (4)

Signal Name Type Description

LOCK#

I/O When the priority agent asserts BPRI# to arbitrate for ownership of

the

rocessor system bus, it will wait until it observes LOCK#

deasserted. This enables symmetric agents to retain ownership of the

processor system bus throughout the bus locked operation and ensure

the atomicity of lock.

PRDY#

O Probe Ready signal used by debug tools to determine processor debug

readiness.

PREQ#

I Probe Request signal used by debug tools to request debug operation

of the processor.

PROCHOT#

I/O As an output, PROCHOT# (Processor Hot) will go active when the

rocessor temperature monitoring sensor detects that the processor

has reached its maximum safe operating temperature. This indicates

that the processor Thermal Control Circuit has been activated, if

enabled. As an input, assertion of PROCHOT# by the system will

activate the TCC, if enabled. TCC will remain active until the system

deasserts PRCCHOT#.

By default PROCHOT# is configured as an output only. Bidirectional

PROCHOT# must be enabled via the BIOS.

This signal may require voltage translation on the motherboard.

PSI#

O Processor Power Status Indicator signal. This signal is asserted when

the processor is in a lower state (HFM and LFM) and lower state

(Deep Sleep and Deeper Sleep).

PWRGOOD

I PWRGOOD (Power Good) is a processor input. The processor

requires this signal as a clean indication that the clocks and power

supplies are stable and within their specifications. ‘Clean’ implies that

the signal will remain low (capable of sinking leakage current),

without glitches, from the time that the power supplies are turned on

until they come within specification. The signal must then transition

monotonically to a high state.

The PWRGOOD signal must be supplied to the processor; it is used

to protect internal circuits against voltage sequencing issues. It should

be driven high throughout the boundary scan operation.

REQ[4:0]

I/O REQ[4:0]#(Request Command) must connect the appropriate pins of

both FSB agents. They are asserted by the current bus owner to the

currently active transaction type. These signals are source

synchronous to ADSTB[0]#.

RESET#

I Asserting the RESET# signal resets the processor to a known state

and invalidates its internal caches without writing back any of their

contents. For a power-on Reset, RESET# must stay active for at least

two milliseconds after VCC and BCLK have reached their proper

specifications.

Signal Name Type Description

RESET#

I On observing active RESET#, both system bus agents will deassert

their outputs within two clocks. All processor straps must be valid

within the specified setup time before RESET# is deasserted.

There is a 55 (normal) on die pull up resistor on this signal.

RS[2:0]#

I RS[2:0]# (Response Status) are driven by the response agent (the

agent

responsible for completion of the current transaction), and must

connect the appropriate pins of both processor system bus agents.

RSVD

Reserved/

No Connect

These pins are RESERVED and must be left unconnected on the

board.

However, it is recommended that routing channels to these pins on

the board be kept open for possible future use. Please refer to the

platform design guides for more details.

SLP#

I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor

to enter the Sleep state. During Sleep state, the processor stops

roviding internal clock signals to all units, leaving only the

Phase-Locked Loop (PLL) still operating. Processors in this state will

not recognize snoops or interrupts. The processor will recognize only

assertion of the RESET# signal, deassertion of SLP#, and removal of

the BCLK input while in Sleep state. If SLP# is deasserted, the

processor exits Sleep state and returns to Stop-Grant state, restarting

its internal clock signals to the bus and processor core units. If

DPSLP# is asserted while in the Sleep state, the processor will exit

the Sleep state and transition to the Deep Sleep state.

SMI#

I SMI# (System Management Interrupt) is asserted asynchronously by

system logic. On accepting a System Management Interrupt, the

rocessor saves the current state and enter System Management Mode

(SMM). An SMI Acknowledge transaction is issued, and the

processor begins program execution from the SMM handler.

If SMI# is asserted during the deassertion of RESET# the processor

will tristate its outputs.

STPCLK#

I STPCLK# (Stop Clock), when asserted, causes the processor to enter

a low power Stop-Grant state. The processor issues a Stop-Grant

Acknowledge transaction, and stops providing internal clock signals

to all processor core units except the system bus and APIC units. The

rocessor continues to snoop bus transactions and service interrupts

while in Stop-Grant state. When STPCLK# is deasserted, the

rocessor restarts its internal clock to all units and resumes execution.

The assertion of STPCLK# has no effect on the bus clock; STPCLK#

is an asynchronous input.

CPU Pin Description (Continued)

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