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8258I N/B Maintenance
8258I N/B Maintenance
5.1 Intel Yonah Processor CPU (3)
Signal Name Type Description
DSTBP[3:0]#
I/O Data strobe used to latch in D[63:0]#.
Signals Associated Strobe
D[15:0]#, DINV[0]# DSTBP[0]#
D[31:16]#, DINV[1]# DSTBP[1]#
D[47:32]#, DINV[2]# DSTBP[2]#
D[63:48]#, DINV[3]# DSTBP[3]#
FERR#/PBE#
O FERR# (Floating-
p
oint Error)/PBE#(Pending Break Event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating point
when the processor detects an unmasked floating-
p
oint error. FERR#
is similar to the ERROR# signal on the Intel 80387 coprocessor, and
is included for compatibility with systems using MS-DOS* type
floating-
p
oint error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending
break event waiting for service. The assertion of FERR#/PBE#
indicates that the processor should be returned to the Normal state.
When FERR#/PBE# is asserted, indicating a break event, it will
remain asserted until STPCLK# is deasserted. Assertion of PREQ#
when STPCLK# is active will also cause an FERR# break event.
For additional information on the pending break event functionality,
including identification of support of the feature and enable/disable
information, refer to Volume 3 of the Intel Architecture Software
Developer’s Manual and AP-485, For termination requirements
please contact your Intel representative.
GTLREF
I GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 VCCP . GTLREF is used by the
AGTL+ receivers to determine if a signal is a logical 0 or logical
1.Plese contact your Intel representative for more information
regarding GTLREF implementation.
HIT#
HITM#
I/O
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Either system bus agent may assert both
HIT# and HITM# together to indicate that it requires a snoop stall,
which can be continued by reasserting HIT# and HITM# together.
IERR#
O IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor system bus. This
transaction may optionally be converted to an external error signal
(e.g., NMI) by system core logic. The processor will keep IERR#
asserted until the assertion of RESET#, BINIT#, or INIT#.
Signal Name Type Description
IGNNE#
I IGNNE# (Ignore Numeric Error) is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol
floating-
p
oint instructions. If IGNNE# is deasserted, the processor
generates an exception on a noncontrol floating-
p
oint instruction if a
previous floating-
p
oint instruction caused an error. IGNNE# has no
effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding
Input/Output Write bus transaction.
INIT#
I INIT#(Initialization), when asserted, resets integer registers inside the
processor without affecting its internal caches or floating-
p
oint
registers, The processor then begins execution at the power-on Reset
vector configured during power-on configuration. The processor
continues to handle snoop requests during INIT# assertion. INIT# is
an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output Write Instruction, it must be valid along
with the TRDY# assertion of the corresponding Input/Output Write
bus transaction, INIT# must connect the appropriate pins of both FSB
agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Selt-Test(BIST).
LINT[1:0]
I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
b
ecomes INTR, a maskable interrupt request signal, and LINT1
b
ecomes NMI, a nonmaskable interrupt. INTR and NMI are
b
ackward compatible with the signals of those names on the Pentium
processor. Both signals are asynchronous.
Both of these signals must be software configured using BIOS
p
rogramming of the APIC register space and used either as
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default
after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK#
I/O LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins of both
p
rocessor system bus agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the
end of the last transaction.
CPU Pin Description (Continued)
CPU Pin Description (Continued)
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