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5.1 Intel Yonah Processor CPU (2)

Signal Name Type Description

D[63:0]#

I/O D[63:0]# (Data) are the data signals. These signals provide a 64-

data path between the processor system bus agents, and must connect

the appropriate pins on both agents. The data driver asserts DRDY#

to indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will thus be driven four

times in a common clock period. D[63:0]# are latched off the falling

edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16

data signals correspond to a pair of one DSTBP# and one DSTBN#.

The following table shows the grouping of data signals to data

strobes and DINV#.

Quad-Pumped Signal Groups

Data Group DSTBN#/DSTBP# DINV#

D[15:0]# 0 0

D[31:16]# 1 1

D[47:32]# 2 2

D[63:48]# 3 3

Furthermore, the DINV# pins determine the polarity of the data

signals. Each group of 16 data signals corresponds to one DINV#

signal. When the DINV# signal is active, the corresponding data

group is inverted and therefore sampled active high.

DBR#

O DBR# (Data Bus Reset) is used only in processor systems where no

debug port is implemented on the system board. DBR# is used by a

debug port interposer so that an in-target probe can drive system

reset. If a debug port is implemented in the system, DBR# is a no

connect. DBR# is not a processor signal.

DBSY#

I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for

driving data on the processor system bus to indicate that the data bus

is in use. The data bus is released after DBSY# is deasserted. This

signal must connect the appropriate pins on both processor system

bus agents.

DEFER#

I DEFER# is asserted by an agent to indicate that a transaction cannot

be guaranteed in-order completion. Assertion of DEFER# is normally

the responsibility of the addressed memory or Input/Output agent.

This signal must connect the appropriate pins of both processor

system bus agents.

Signal Name Type Description

DINV[3:0]#

I/O DINV[3:0]# (Data Bus Inversion) are source synchronous and

indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals

are activated when the data on the data bus is inverted. The bus agent

will invert the data bus signals if more than half the bits, within the

covered group, would change level in the next cycle.

DINV[3:0]# Assignment To Data Bus

Bus Signal Data Bus Signals

DINV[3]# D[63:48]#

DINV[2]# D[47:32]#

DINV[1]# D[31:16]#

DINV[0]# D[15:0]#

DPRSTP#

I DPRSTP# when asserted on the platform causes the processor to

transition from the Deep Sleep State to the Deeper Sleep Stated. In

order to return to the Deep Sleep State, DPRSTP# must be deasserted.

DPRSTP# is driven by the Intel ICH7M chipset.

DPSLP#

I DPSLP# when asserted on the platform causes the processor to

transition from the Sleep state to the Deep Sleep state. In order to

return to the Sleep state, DPSLP# must be deasserted. DPSLP# is

driven by the ICH7M chipset.

DRDY#

I/O DRDY# (Data Ready) is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-common

clock data transfer, DRDY# may be deasserted to insert idle clocks.

This signal must connect the appropriate pins of both processor

system bus agents.

DSTBN[3:0]#

I/O Data strobe used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#, DINV[0]# DSTBN[0]#

D[31:16]#, DINV[1]# DSTBN[1]#

D[47:32]#, DINV[2]# DSTBN[2]#

D[63:48]#, DINV[3]# DSTBN[3]#

CPU Pin Description (Continued)

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