Service manual

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8258I N/B Maintenance
8258I N/B Maintenance
5. Pin Descriptions of Major Components
5.1 Intel Yonah Processor CPU (1)
CPU Pin Description
CPU Pin Description (Continued)
Signal Name Type Description
A[31:3]#
I/O A[31:]#(Address) define a 2*32- byte physical memory address
space. In sub-
p
hase 1 of the address phase, these pins transmit the
address of a transaction. Must connect the appropriate pins of both
agents on the Intel Core TM Duo processor and the Intel Core TM
Solo processor FSB. A[31:3]# are source synchronous signals and are
latched into the receiving buffers by ADSTB[1:0]#. Address signals
are used as straps which are sampled before RESET# is deasserted.
A20M#
I If A20M#(Address-20 Mask) is asserted, the processor masks
p
hysical address bit 20(A20#) before looking up a line in any internal
cache and before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor’s address wrap-around
at the 1-Mbyte boundary. Assertion of A20M# is only supported in
real mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding
Input/Output Write bus transaction.
ADS#
I/O ADS#(Address Strobe) is asserted to indicate the validity of the
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus
agents observe the ADS# activation to begin parity checking, protocol
checking, address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction.
ADSTB#
I/O Address strobes are used to latch A[31:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as shown
below.
Signals Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[31:17]# ADSTB[1]#
BCLK[1:0]
I The differential pair BCLK (Bus Clock) determines the system bus
frequency. All processor system bus agents must receive these signals
to drive their outputs and latch their inputs.
BNR#
I/O BNR# (Block Next Request) is used to assert a bus stall by any bus
agent that is unable to accept new bus transactions. During a bus stall,
the current bus owner cannot issue any new transactions.
Signal Name Type Description
BPM[2:1]#
BPM[3,0]#
I/O BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor that indicate the
status of breakpoints and programmable counters used for monitoring
processor performance. BPM[3:0]# should connect the appropriate
p
ins of all Intel Pentium M processor system bus agents. This
includes debug or performance monitoring tools.
BPRI#
I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor system bus. It must connect the appropriate pins of both
p
rocessor system bus agents. Observing BPRI# active (as asserted by
the priority agent) causes the other agent to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The
p
riority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by deasserting BPRI#.
BR0#
I/O BR0# is used by the processor to request the bus. The arbitration is
done between the Intel Pentium M processor (Symmetric Agent) and
the Mobile Intel 945 Express chipset family (High Priority Agent).
BSEL[2:0]
O BSEL[2:0] (Bus SELECT) are used to select the processor input
clock frequency. The table defines the possible combinations of the
signals and the frequency associated with each combination. The
required frequency is determined by the processor, chipset and clock
synthesizer. All agents must operate at the same frequency. The
p
rocessor operates at 667 MHz or 533 MHz system bus frequency
(166MHz or 133MHz BCLK[1:0] frequency, respectively).
BSE[2:0] Encoding for BCLK Frequency
BSEL[2] BSEL[1] BSE[0]
BCLK
Frequency
L L L Reserved
L L H 133MHz
L H L Reserved
L H H 166MHz
COMPP3:0]
Analog COMP[3:0] must be terminated on the system board using precision
(1% tolerance) resistors. Refer to the platform design guides for more
implementation details.
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