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8258I N/B Maintenance
8258I N/B Maintenance
1.5 Appendix 1: Intel ICH7-M GPIO Definitions-1
Pin name Current Define
Default
Input/output Function Power Well
GPIO0 PM_BMBUSY# I Bus Master busy CORE
GPIO1 PCI_REQ5# I X CORE
GPIO2 PCI_INTE# I PCI interrupt for
LAN
CORE
GPIO3 PCI_INTF# I X CORE
GPIO4 PCI_INTG# I X CORE
GPIO5 PCI_INTH# I X CORE
GPIO6 SMB_SEL I ECO Function CORE
GPIO7 SCI# I System Control
Interrupt
CORE
GPIO8 EXTSMI# I SMI signal for
chipset
RESUME
GPIO9 X I X RESUM E
GPIO10 X I X RESUM E
GPIO11 SMBALERT# Native SMBus alert RESUME
GPIO12 X I X RESUM E
GPIO13 X I X RESUM E
GPIO14 X I X RESUM E
GPIO15 X I X RESUM E
GPIO16 DPRSLPVR O Lo wer p ower in
deeper sleep
CORE
GPIO17 X O X CORE
GPIO18 STOP_PCI# O PCI s top CORE
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