User`s manual

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BIOS Setup

MS-7582

Chapter 3

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BIOS Setup

MS-7582

Chapter 3

DIMM1~4 Memory SPD Information

Press <Enter> to enter the sub-menu. The sub-menu displays the informations of

installed memory.

Current DRAM Channel1~4 Timing

It shows the installed DRAM Timing. Read-only.

DRAM Timing Mode

Select whether DRAM timing is controlled by the SPD (Serial Presence Detect) EE-

PROM on the DRAM module. Setting to [Auto] enables DRAM timings and the following

“Advance DRAM Conguration” sub-menu to be determined by BIOS based on the con-

gurations on the SPD. Selecting [Manual] allows users to congure the DRAM timings

and the following related “Advance DRAM Conguration” sub-menu manually.

Advance DRAM Conguration

When the DRAM Timing Mode is set to [Manual], this sub-menu will available. Press

<Enter> to enter the sub-menu.

CH1/ CH2 1T/2T Memory Timing

This item controls the SDRAM command rate. Select [1N] makes SDRAM signal

controller to run at 1N (N=clock cycles) rate. Selecting [2N] makes SDRAM signal

controller run at 2N rate.

CH1/ CH2 CAS Latency (CL)

This controls the CAS latency, which determines the timing delay (in clock cycles)

before SDRAM starts a read command after receiving it.

CH1/ CH2 tRCD

When DRAM is refreshed, both rows and columns are addressed separately. This

setup item allows you to determine the timing of the transition from RAS (row ad-

dress strobe) to CAS (column address strobe). The less the clock cycles, the faster

the DRAM performance.

CH1/ CH2 tRP

This setting controls the number of cycles for Row Address Strobe (RAS) to be

allowed to precharge. If insucient time is allowed for the RAS to accumulate its

charge before DRAM refresh, refresh may be incomplete and DRAM may fail to

retain data. This item applies only when synchronous DRAM is installed in the sys-

tem.

CH1/ CH2 tRAS

This setting determines the time RAS takes to read from and write to memory cell.

CH1/ CH2 tRFC

This setting determines the time RFC takes to read from and write to a memory

cell.

CH1/ CH2 tWR

Minimum time interval between end of write data burst and the start of a precharge

command. Allows sense ampliers to restore data to cells.

CH1/ CH2 tWTR

Minimum time interval between the end of write data burst and the start of a col-

umn-read command. It allows I/O gating to overdrive sense ampliers before read

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