Datasheet

Intel
®
82845G/82845GL/82845GV GMCH Datasheet 99
Register Description
3.5.3.14 ROMADR—Video BIOS ROM Base Address Registers (Device 2)
Address Offset: 30–33h
Default Value: 00000000h
Access: R/W, RO
Size: 32 bits
The IGD does not use a separate BIOS ROM; therefore, this register is hardwired to zeros.
3.5.3.15 CAPPOINT—Capabilities Pointer Register (Device 2)
Address Offset: 34h
Default Value: D0h
Access: RO
Size: 8 bits
3.5.3.16 INTRLINE—Interrupt Line Register (Device 2)
Address Offset: 3Ch
Default Value: 00h
Access: R/W
Size: 8 bits
Bit Description
31:18 ROM Base Address—RO. Hardwired to zeros.
17:11
Address Mask—RO. Hardwired to zeros to indicate 256-KB address range.
10:1 Reserved. Hardwired to zeros.
0
ROM BIOS Enable—RO. Hardwired to 0 to indicate that the ROM is not accessible.
Bit Description
7:0
Capabilities Pointer Value. This field contains an offset into the function’s PCI Configuration Space
for the first item in the New Capabilities Linked List, the ACPI registers at address D0h.
Bit Description
7:0
Interrupt Connection. This field is used to communicate interrupt line routing information. POST
software writes the routing information into this register as it initializes and configures the system.
The value in this register indicates which input of the system interrupt controller that the device’s
interrupt pin is connected to. This register is needed for Plug N Play software.
Settings of this register field has no effect on GMCH operation as there is no hardware functionality
associated with this register, other than the hardware implementation of the R/W register itself.