Datasheet

Intel

82845G/82845GL/82845GV GMCH Datasheet 91

The bit field definitions for VGAEN and MDAP are detailed in Table 3-4.

3.5.2.22 ERRCMD1—Error Command Register (Device 1)

Address Offset: 40h

Default Value: 00h

Access: R/W

Size: 8 bits

Table 3-4. VGAEN and MDAP Bit Definitions

VGAEN MDAP Description

0 0 All References to MDA and VGA space are routed to hub interface.

0 1 Illegal combination

All VGA references are routed to this bus. MDA references are routed to the hub

interface.

1 1 All VGA references are routed to this bus. MDA references are routed to hub interface.

Bit Description

7:1 Reserved.

SERR on Receiving Target Abort (SERTA). SERR messaging for Device 1 is globally enabled in

the PCICMD1 register.

0 = Disable. The GMCH does not assert an SERR message upon receipt of a target abort on

PCI_B.

1 = Enable. The GMCH generates an SERR message over the hub interface upon receiving a

target abort on PCI_B.