Datasheet

Intel

82845G/82845GL/82845GV GMCH Datasheet 87

3.5.2.17 MBASE1—Memory Base Address Register (Device 1)

Address Offset: 20–21h

Default Value: FFF0h

Access: R/W

Size: 16 bits

This register controls the processor to PCI_B non-prefetchable memory access routing based on

the following formula:

MEMORY_BASE ≤ address ≤ MEMORY_LIMIT

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits

A[31:20] of the 32-bit address. The bottom four bits of this register are read only and return zeros

when read. This register must be initialized by the configuration software. For the purpose of

address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory

address range will be aligned to a 1-MB boundary.

Bit Description

15:4

Memory Address Base (MBASE). This field corresponds to A[31:20] of the lower limit of the

memory range that will be passed by the Device 1 bridge to AGP/PCI_B.

3:0 Reserved.