Datasheet

Intel
®
82845G/82845GL/82845GV GMCH Datasheet 83
Register Description
3.5.2.8 MLT1—Master Latency Timer Register (Device 1)
Address Offset: 0Dh
Default Value: 00h
Access: RO, R/W
Size: 8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a
read/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.”
3.5.2.9 HDR1—Header Type Register (Device 1)
Address Offset: 0Eh
Default Value: 01h
Access: RO
Size: 8 bits
This register identifies the header layout of the configuration space. No physical register exists at
this location.
3.5.2.10 PBUSN1—Primary Bus Number Register (Device 1)
Address Offset: 18h
Default Value: 00h
Access: RO
Size: 8 bits
This register identifies that “virtual” PCI-to-PCI bridge is connected to bus #0.
Bit Description
7:3
Scratchpad MLT (NA7.3). These bits return the value with which they are written; however, they
have no internal function and are implemented as a scratchpad merely to avoid confusing software.
2:0 Reserved.
Bit Description
7:0
Header Type Register (HDR). This read only field always returns 01 to indicate that GMCH Device 1
is a single function device with bridge header layout.
Bit Description
7:0
Primary Bus Number (BUSN). Configuration software typically programs this field with the number
of the bus on the primary side of the bridge. Since Device 1 is an internal device and its primary bus
is always 0, these bits are read only and are hardwired to 0.