Datasheet

Register Description
74 Intel
®
82845G/82845GL/82845GV GMCH Datasheet
3.5.1.33 ERRSTS—Error Status Register (Device 0)
Address Offset: C8–C9h
Default Value: 0000h
Access: R/WC
Size: 16 bits
This register is used to report various error conditions via the SERR HI messaging mechanism. An
SERR HI message is generated on a zero to one transition of any of these flags (if enabled by the
ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is
enabled and generated.
Note: Software clears bits in this register by writing a 1 to the bit position.
Bit Description
15:10 Intel Reserved.
9
Non-DRAM Lock Error (NDLOCK).
1 = The GMCH has detected a lock operation to memory space that did not map into SDRAM.
8
Software Generated SMI Flag.
1 = This indicates the source of an SMI was a Software SMI Trigger.
7 Intel Reserved.
6
SERR on HI Target Abort (TAHLA).
1 = GMCH has detected that an GMCH originated hub interface cycle was terminated with a Target
Abort completion packet or special cycle.
5
GMCH Detects Unimplemented HI Special Cycle (HIAUSC).
1 = GMCH detected an Unimplemented Special Cycle on the hub interface.
4
AGP Access Outside of Graphics Aperture Flag (OOGF).
1 = AGP access occurred to an address that is outside of the graphics aperture range.
3
Invalid AGP Access Flag (IAAF).
1 = AGP access was attempted outside of the graphics aperture and either to the 640 KB –1 MB
range or above the top of memory.
2
Invalid Graphics Aperture Translation Table Entry (ITTEF).
1 = An invalid translation table entry was returned in response to an AGP access to the graphics
aperture.
1:0 Intel Reserved.