Datasheet

Register Description
62 Intel
®
82845G/82845GL/82845GV GMCH Datasheet
3.5.1.18 DRT—DRAM Timing Register (Device 0)
Address Offset: 78–7Bh
Default Value: 00000000h
Access: Read/Write
Size: 32 bits
This register controls the timing of the DRAM controller.
Bit Description
31:18 Intel Reserved.
17:15
DRAM Idle Timer. This field determines the number of clocks the SDRAM controller will remain in
the idle state before it begins pre-charging all pages.
000 =
Infinite
001 = 0
010 = 8 DRAM clocks
011 = 16 DRAM clocks
100 = 64 DRAM clocks
Others = reserved
14:12 Intel Reserved.
11
Activate to Precharge Delay (tRAS), MAX. This bit controls the maximum number of clocks that a
DRAM (SDR or DDR) bank can remain open. After this time period, the DRAM controller will
guarantee to pre-charge the bank. Note that this time period may or may not be set to overlap with
time period that requires a refresh to happen.
The DRAM controller incudes a separate tRAS-MAX counter for every supported bank. With a
maximum of four row and four banks per row, there are 16 counters.
0 = 120
µs
1 = Reserved.
10:9
Activate to Precharge delay (tRAS), MIN. This bit controls the number of DRAM clocks for tRAS
minimum.
00 = 8 Clocks
01 = 7 Clocks
10 = 6 Clocks
11 = 5 Clocks
8:7 Intel Reserved.
6:5
CAS# Latency (tCL).
Encoding SDR CL DDR CL
00 Reserved 2.5
01 3 2
10 2 Reserved
11 Reserved Reserved
4 Intel Reserved.
3:2
DRAM RAS# to CAS# Delay (tRCD). This bit controls the number of clocks inserted between a row
activate command and a read or write command to that row.
01 = 3 DRAM Clocks
10 = 2 DRAM Clocks
11 = Reserved
1:0
DRAM RAS# Precharge (tRP). This bit controls the number of clocks that are inserted between a
row precharge command and an activate command to the same row.
00 = Intel Reserved
01 = 3 DRAM Clocks
10 = 2 DRAM Clocks
11 = Reserved