Datasheet

60 Intel

82845G/82845GL/82845GV GMCH Datasheet

3.5.1.16 DRB[0:3]—DRAM Row Boundary Register (Device 0)

Address Offset: 60–63h (64h–6Fh Reserved)

Default Value: 01h

Access: Read/Write

Size: 8 bits

The DRAM Row Boundary Register defines the upper boundary address of each DRAM row with

a granularity of 32 MB. Each row has its own single-byte DRB register. For example, a value of 1

in DRB0 indicates that 32 MB of DRAM has been populated in the first row. Since the GMCH

supports a total of four rows of memory, only DRB[0:3] are used.

Row0: 60h

Row1: 61h

Row2: 62h

Row3: 63h

64h–6Fh: Reserved

DRB0 = Total memory in row0 (in 32-MB increments)

DRB1 = Total memory in row0 + row1 (in 32-MB increments)

DRB2 = Total memory in row0 + row1 + row2 (in 32-MB increments)

DRB3 = Total memory in row0 + row1 + row2 + row3 (in 32-MB increments)

Each Row is represented by a byte. Each byte has the following format.

Bit Description

7:0

DRAM Row Boundary Address. This 8-bit value defines the upper and lower addresses for each

SDRAM row. This 8-bit value is compared against a set of address lines to determine the upper

address limit of a particular row.