Datasheet

Intel

82845G/82845GL/82845GV GMCH Datasheet 51

3.5.1.3 PCICMD—PCI Command Register (Device 0)

Address Offset: 04–05h

Default Value: 0006h

Access: RO, R/W

Size: 16 bits

Since GMCH Device 0 does not physically reside on PCI_A, many of the bits are not implemented.

Bit Description

15:10 Reserved.

Fast Back-to-Back Enable (FB2B)—RO. Hardwired to 0. This bit controls whether or not the master

can do fast back-to-back write. Since Device 0 is strictly a target, this bit is not implemented.

SERR Enable (SERRE)—R/W. This bit is a global enable bit for Device 0 SERR messaging. The

GMCH does not have an SERR signal. The GMCH communicates the SERR condition by sending

an SERR message over HI to the ICH4.

0 = Disable. The GMCH does not generate the SERR message for Device 0.

1 = Enable. GMCH is enabled to generate SERR messages over the hub interface for specific

Device 0 error conditions that are individually enabled in the ERRCMD register. The error status

is reported in the ERRSTS and PCISTS registers.

NOTE: This bit only controls SERR messaging for the Device 0. Devices 1has its own SERRE bits

to control error reporting for error conditions occurring on their respective devices. The

control bits are used in a logical OR manner to enable the SERR HI message mechanism.

Address/Data Stepping Enable (ADSTEP)—RO. Hardwired to 0. Not implemented.

Parity Error Enable (PERRE)—RO. Hardwired to 0. PERR# is not implemented by the GMCH.

VGA Palette Snoop Enable (VGASNOOP)—RO. Hardwired to 0. Not implemented.

Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0. The GMCH will never issue

memory write and invalidate commands.

Special Cycle Enable (SCE)—RO. Hardwired to 0. The GMCH does not implement this bit.

Bus Master Enable (BME)—RO. Hardwired to 1. The GMCH is always enabled as a master on the

hub interface.

Memory Access Enable (MAE)—RO. Hardwired to 1. Not implemented. The GMCH always allows

access to main memory.

I/O Access Enable (IOAE)—RO. Hardwired to 0. Not implemented.