Datasheet

Register Description
48 Intel
®
82845G/82845GL/82845GV GMCH Datasheet
3.5 Intel
®
GMCH Internal Device Registers
3.5.1 DRAM Controller/Host-Hub Interface Device Registers
(Device 0)
The DRAM controller and host-hub interface registers are in Device 0. This section contains the
PCI configuration registers listed in order of ascending offset address. Table 3-1 provides the
register address map for this device.
Table 3-1. DRAM Controller/Host-Hub Register Address Map (Device 0) (Sheet 1 of 2)
Address
Offset
Symbol Register Name Default Value Access
00–01h VID Vendor Identification 8086h RO
02–03h DID Device Identification 2560h RO
04–05h PCICMD PCI Command Register 0006h RO, R/W
06–07h PCISTS PCI Status Register 0090h RO, R/WC
08h RID Revision Identification
see register
description
RO
09 — Intel Reserved — —
0Ah SUBC Sub-Class Code 00h RO
0Bh BCC Base Class Code 06h RO
0Ch — Intel Reserved — —
0Dh MLT Master Latency Timer 00h RO
0Eh HDR Header Type 00h RO
0Fh — Intel Reserved — —
10–13h APBASE Aperture Base Configuration 00000008h RO, R/W
14–2Bh — Intel Reserved — —
2C–2Dh SVID Subsystem Vendor Identification 0000h R/WO
2E–2Fh SID Subsystem Identification 0000h R/WO
30–33h — Intel Reserved — —
34h CAPPTR Capabilities Pointer E4h RO
35–50h — Intel Reserved — —
51h AGPM AGP Miscellaneous Configuration 00h R/W
52h GC Graphics Control 0000_1000b R/W
53–5Fh — Intel Reserved — —
60–63h DRB[0:3] DRAM Row Boundary (4 registers) 01h RW
64–6Fh — Intel Reserved — —
70–71h DRA[0:3] DRAM Row Attribute (4 registers) 00h RW
72–77h — Intel Reserved — —
78–7Bh DRT DRAM Timing Register 00000000h RW
7C–7Fh DRC DRAM Controller Mode 00000000h RW, RO
80–8Fh — Intel Reserved — —