Datasheet

Intel
®
82845G/82845GL/82845GV GMCH Datasheet 27
Signal Description
SRAS# SCKE_0 AK28 SDQ_3 SDQ_4 AP5
SCS_2# SCS_3# AK30 SDQ_13 SDQ_6 AP6
SDQ_63 SDQ_31 AK34 SDQ_15 SDQ_39 AP8
SDQ_62 SDQ_30 AK35 SCMDCLK_4 SCMDCLK_0 AP9
SDQ_58 SDQ_62 AK36 SDQ_11 SDQ_40 AR10
SCKE_3 SCAS# AL13 SDQ_21 SDQ_42 AR12
SMAA_11 SCS_5# AL15 SDQ_22 SDQ_12 AR14
SMAA_5 SRAS# AL17 SDQ_28 SDQ_46 AR16
SMAA_4 SMAA_3 AL19 SDM_3 SDQ_15 AR18
SCMDCLK_0 SMAA_4 AL21 SDQS_0 Reserved AR2
SRCVEN_IN# SRCVEN_IN# AL23 SDQ_31 SDM_5 AR20
SMAA_0 SMAA_10 AL25 SDQ_32 SDM_2 AR22
SCS_0# SCS_2# AL29 SDQS_4 Reserved AR24
SCMDCLK_2# SCMDCLK_7 AL33 SDQ_39 SDQ_49 AR26
SDM_7 SDQ_29 AL34 SDQ_45 SDQ_51 AR28
SDQS_7 Reserved AL36 SDQ_42 SDQ_53 AR30
SM_VREF SM_VREF AM2 SDQ_48 SDQ_55 AR32
SCMDCLK_2 SCMDCLK_6 AM34 SDM_6 SDQ_25 AR34
SDQ_61 SDQ_28 AM35 SDQ_50 SDQ_58 AR36
SDQ_57 SDQ_61 AM36 SDQ_6 SDQ_3 AR4
SCMDCLK_1 SCMDCLK_4 AN11 SDQ_9 SDQ_5 AR6
SCKE_1 Reserved AN13 SDM_1 SDQ_38 AR8
SMAA_12 SCS_1# AN15 SDQ_20 SDQ_41 AT10
SMAA_8 Reserved AN17 SDQ_17 SDQ_10 AT11
SMAB_4 SMAA_2 AN19 SDQS_2 Reserved AT12
SDQ_4 SDQ_32 AN4 SDQ_18 SDQ_11 AT13
SCMDCLK_3# SMAA_7 AN21 SDQ_19 SDQ_44 AT14
SMAB_2 SMAA_9 AN23 SDQ_24 SDQ_13 AT15
SMAA_1 SMAA_11 AN25 SDQ_29 SDQ_14 AT16
SBA_0 SCKE_2 AN27 SDQS_3 Reserved AT17
SCAS# SCKE_1 AN29 SDQ_26 SDM_0 AT18
SCS_3# SCS_7# AN31 SDQ_27 SDM_1 AT19
SCMDCLK_5# SCMDCLK_3 AN34 SDQ_36 SDM_6 AT22
SDQ_56 SDQ_60 AN36 SDQ_37 SDM_7 AT23
SDQ_0 SDQ_0 AN4 SDM_4 SDQ_16 AT24
SCMDCLK_4# SCMDCLK_1 AN9 SDQ_38 SDQ_17 AT25
SDQ_16 SDQ_9 AP10 SDQ_35 SDQ_18 AT26
SCMDCLK_1# SCMDCLK_5 AP11 SDQ_44 SDQ_19 AT27
SDM_2 SDQ_43 AP12 SDQ_41 SDQ_20 AT28
Table 2-1. DDR-to-SDR Signal Mapping (Sheet 2 of 3)
DDR Ball Name SDR Ball Name Ball # DDR Ball Name SDR Ball Name Ball #