Datasheet

Signal Description
26 Intel
®
82845G/82845GL/82845GV GMCH Datasheet
2.2.2 SDR SDRAM Interface
The SDR interface signals are multiplexed with the DDR signals. At power up the functional strap
setting on MEMSEL determines whether the memory interface is set up for DDR or SDR. The
DDR-to-SDR signal mapping is provided in Table 2-1.
Signal Name Type Description
SCK_[7:0] O LVTTL SDR System Memory Clock: These signals provide the 133 MHz SDRAM
clocks for the DIMMs. Note that there are two SCK per SDRAM row.
SCS_[7:0]# O
LVTTL
Chip Select: These pins select the particular SDRAM components during the
active state. Note that there are two SCS# per SDRAM row. These signals can
be toggled on every rising system memory clock edge.
SMAA_[12:0] O
LVTTL
Memory Address: These signals provide the multiplexed row and column
address to SDRAM.
SBA_[1:0] O
LVTTL
Bank Select (Bank Address): The bank select signals and memory address
signals combine to address every possible location within an SDRAM device.
SRAS# O
LVTTL
Row Address Strobe: SRAS# is used with SCAS# and SWE# (along with
SCS#) to define the SDRAM commands.
SCAS# O
LVTTL
Column Address Strobe: SCAS# is used with SRAS# and SWE# (along with
SCS#) to define the SDRAM commands.
SWE# O
LVTTL
Write Enable: SWE# is used with SCAS# and SRAS# (along with SCS#) to
define the SDRAM commands.
SDQ_[63:0] I/O
LVTTL
Data Lines: SDQ_[63:0] interface to the SDRAM data bus.
SDM_[7:0] O LVTTL Data Mask: When activated during writes, the corresponding data groups in the
SDRAM are masked. There is one SDM for every eight data lines.
SCKE_[3:0] O
LVTTL
Clock Enable: These signals are used for placing all SDRAM rows into and out
of self-refresh during Suspend-to-RAM. SCKE is also used to dynamically
power down inactive SDRAM rows. There is one SCKE per SDRAM row.
SRDCLK_OUT O
LVTTL
Read Clock Out: Feedback testpoint signal used to emulate source-synch
clocking for reads. This pin should be connect to SRDCLK_IN through an un-
populated backside resistor site.
SRDCLK_IN I
LVTTL
Read Clock Input: Feedback testpoint signal used to emulate source-synch
clocking for reads.
Table 2-1. DDR-to-SDR Signal Mapping (Sheet 1 of 3)
DDR Ball Name SDR Ball Name Ball # DDR Ball Name SDR Ball Name Ball #
SMXRCOMP SMXRCOMP AF10 SWE# SCKE_3 AP29
SMYRCOMP SMYRCOMP AJ34 SDQ_5 SDQ_1 AP3
SDQ_59 SDQ_63 AJ36 SDQ_43 SDQ_54 AP30
SCKE_2 SWE# AK14 SCS_1# SCS_6# AP31
SMAA_9 SCS_4# AK16 SDQ_52 SDQ_24 AP32
SMAB_5 SCS_0# AK18 SCMDCLK_5 SCMDCLK_2 AP33
SMAA_3 SMAA_0 AK20 SDQ_54 SDQ_57 AP34
SCMDCLK_0# SMAA_5 AK22 SDQ_51 SDQ_27 AP35
SRCVEN_OUT# SRCVEN_OUT# AK24 SDQ_60 SDQ_59 AP36
SMAA_10 SBA_0 AK26 SDM_0 SDQ_2 AP4