Datasheet
System Address
144 Intel
®
82845G/82845GL/82845GV GMCH Datasheet
Table 5-2 details the location and attributes of the regions. Enabling/disabling these ranges are
described in the GMCH Control Register Device 0 (GC).
Extended SMRAM Address Range (HSEG and TSEG)
The HSEG and TSEG SMM transaction address spaces reside in this extended memory area.
HSEG
SMM-mode processor accesses to enabled HSEG are remapped to 000A0000h–000BFFFFh. Non-
SMM-mode processor accesses to enabled HSEG are considered invalid are terminated
immediately on the PSB. The exceptions to this rule are Non-SMM-mode Write Back cycles that
are remapped to SMM space to maintain cache coherency. AGP and hub interface-originated
cycles to enabled SMM space are not allowed. Physical SDRAM behind the HSEG transaction
address is not remapped and is not accessible.
TSEG
TSEG can be up to 1 MB in size and is at the top of physical memory. SMM-mode processor
accesses to enabled TSEG access the physical SDRAM at the same address. Non-SMM-mode
processor accesses to enabled TSEG are considered invalid and are terminated immediately on the
PSB. The exceptions to this rule are Non-SMM-mode Write Back cycles that are directed to the
physical SMM space to maintain cache coherency. AGP and hub interface-originated cycles to
enabled SMM space are not allowed.
The size of the SMRAM space is determined by the USMM value in the SMRAM register. When
the extended SMRAM space is enabled, non-SMM processor accesses and all other accesses in this
range are forwarded to the hub interface. When SMM is enabled, the amount of memory available
to the system is equal to the amount of physical SDRAM minus the value in the TSEG register.
Table 5-2. Pre-allocated Memory
Memory Segments Attributes Comments
00000000h–03E7FFFFh R/W Available System Memory 62.5 MB
03E80000h–03F7FFFFh R/W
Pre-allocated Graphics VGA memory.
1 MB (or 512 K or 8 MB) when IGD is
enabled.
03F80000h–03FFFFFFh
SMM Mode Only - processor
reads
TSEG Address Range
03F80000h–03FFFFFFh
SMM Mode Only - processor
reads
TSEG Pre-allocated Memory