Datasheet

Intel
®
82845G/82845GL/82845GV GMCH Datasheet 137
Functional Description
4.6.5 Monitor State Control
• D0 (On): In this state, both HSYNC and VSYNC are pulsed.
• D1 (Standby): The D1 monitor state is the standby mode. VSYNC is pulsed.
• D2 (Suspend): The D2 monitor state is the suspend mode. HSYNC is pulsed.
• D3 (Off): The D3 power state is the off mode. HSYNC and VSYNC are not pulsed in this
state.
4.7 Clocking
Figure 4-2 shows a block diagram of an 845G chipset-based system. The GMCH has the following
clocks:
• 100/133 MHz, Spread spectrum, Low voltage (0.7 V) Differential HCLKP/HCLKN for PSB
• 66.667 MHz, Spread spectrum, 3.3 V GCLKIN for hub interface and AGP
• 48 MHz, Non-Spread spectrum, 3.3 V DREFCLK for the Display frequency syntheses
• Up to 85 MHz, 1.5 V DVOBC_CLKINT for TV-Out mode
The GMCH has inputs for a low voltage, differential pair of clocks called HCLKP and HCLKN.
These pins receive a host clock from the external clock synthesizer. This clock is used by the host
interface and system memory logic. The graphics engine also uses this clock.
The graphics core and display interfaces are asynchronous to the rest of the GMCH. The Graphics
core runs at 200 MHz. The display PLL uses the Non-Spread Spectrum 48 MHz input to generate a
frequency range of 12 MHz–350 MHz.