Datasheet

Intel
®
82845G/82845GL/82845GV GMCH Datasheet 115
Functional Description
4.3.2 PCI Semantic Transactions on AGP
The GMCH accepts and generates PCI semantic transactions on the AGP bus. The GMCH
guarantees that PCI semantic accesses to SDRAM are kept coherent with the processor caches by
generating snoops to the processor bus.
4.3.2.1 GMCH Initiator and Target PCI Operations
Table 4-7 summarizes PCI target operation support of the GMCH for AGP/PCI_B bus initiators.
The cycles can be either destined to main memory or the hub interface bus.
NOTE: N/A refers to a function that is not applicable
As a target of an AGP/PCI cycle, the GMCH only supports the following transactions:
Memory Read: The GMCH issues one snoop and the entire cache line of read data is buffered. If
a memory read bursts across the cache line, another snoop is issued but the transaction will be
disconnected on the cache line boundary. Subsequent memory read transaction hitting the cache
line buffer return data from the buffer.
Table 4-7. PCI Commands Supported by GMCH When Acting As a PCI Target
PCI Command GC/BE[3:0]# Encoding GMCH
Cycle Destination
Response As PCI
Target
Interrupt Acknowledge 0000 N/A No Response
Special Cycle 0001 N/A No Response
I/O Read 0010 N/A No Response
I/O Write 0011 N/A No Response
Reserved 0100 N/A No Response
Reserved 0101 N/A No Response
Memory Read
0110 Main Memory Read
0110 Hub Interface No Response
Memory Write
0111 Main Memory Posts Data
0111 Hub Interface No Response
Reserved 1000 N/A No Response
Reserved 1001 N/A No Response
Configuration Read 1010 N/A No Response
Configuration Write 1011 N/A No Response
Memory Read Multiple
1100 Main Memory Read
1100 Hub Interface No Response
Dual Address Cycle 1101 N/A No Response
Memory Read Line
1110 Main Memory Read
1110 Hub Interface No Response
Memory Write and Invalidate
1111 Main Memory Posts Data
1111 Hub Interface No Response