Datasheet

Functional Description
110 Intel
®
82845G/82845GL/82845GV GMCH Datasheet
4.2.5 DRAM Performance Description
The overall memory performance is controlled by the DRAM timing register, pipelining depth used
in the GMCH, memory speed grade, and the type of SDRAM used in the system. In addition, the
exact performance in a system is also dependent on the total memory supported, external buffering,
and memory array layout. The most important contribution to overall performance by the system
memory controller is to minimize the latency required to initiate and complete requests to memory,
and to support the highest possible bandwidth (full streaming, quick turnarounds). One measure of
performance is the total flight time to complete a cache line request. A true discussion of
performance involves the entire chipset, not just the system memory controller.
Table 4-5. Address Translation and Decoding
Tech (Mbit)
Configuration
Row/Page Size
(Mbyet)
R/C/B
Addr
BA1 BA0
A12
A11
A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
64
1 Meg
x 16
x 4 bks
32
12
x 8
x 2
R
o
w
24 11 12 x[26] 15 14 13 24 23 22 21 20 19 18 17 16
64
2 Meg
x 8
x 4 bks
64
12
x 9
x 2
R
o
w
25 13 12
x[26] 15 14 25 24 23 22 21 20 19 18 17 16
128
2 Meg
x 16
x 4 bks
64
12
x 9
x 2
R
o
w
25 13 12
x[26] 15 14 25 24 23 22 21 20 19 18 17 16
256
4 Meg
x 16
x 4 bks
128
13
x 9
x 2
R
o
w
26 13 12 26 15 14 25 24 23 22 21 20 19 18 17 16
128
4 Meg
x 8
x 4 bks
128
12
x 10
x 2
R
o
w
26 14 13
x[27] 15 26 25 24 23 22 21 20 19 18 17 16
256
8 Meg
x 8
x 4 bks
256
13
x 10
x 2
R
o
w
27 14 13 27 15 26 25 24 23 22 21 20 19 18 17 16