Datasheet

Intel
®
82845G/82845GL/82845GV GMCH Datasheet 101
Register Description
3.5.3.21 PMCAP—Power Management Capabilities Register (Device 2)
Address Offset: D2h−D3h
Default Value: 0021h
Access: RO
Size: 16 bits
3.5.3.22 PMCS—Power Management Control/Status Register (Device 2)
Address Offset: D4h−D5h
Default Value: 0000h
Access: R/W, RO
Size: 16 bits
Bit Description
15:11
PME Support. Hardwired to 0. This field indicates the power states in which the IGD may assert
PME#. The IGD does not assert the PME# signal.
10
D2. Hardwired to 0. The D2 power management state is not supported.
9
D1. Hardwired to 0. The D1 power management state is not supported.
8:6 Reserved. Read as zeros.
5
Device Specific Initialization (DSI). Hardwired to 1 to indicate that special initialization of the IGD is
required before generic class device driver is to use it.
4
Auxiliary Power Source. Hardwired to 0.
3
PME Clock. Hardwired to 0. The IGD does not support PME# generation.
2:0
Version. Hardwired to 001b to indicate there are 4 bytes of power management registers
implemented.
Bit Description
15 PME_Status—RO. Hardwired to 0. The IGD does not support PME# generation from D3 (cold).
14:13
Data Scale (Reserved)—RO. Hardwired to 0. The IGD does not support data register.
12:9
Data_Select (Reserved)—RO. Hardwired to 0. The IGD does not support data register.
8
PME_En—RO. Hardwired to 0. PME# assertion from D3 (cold) is disabled.
7:2 Reserved.
Always returns 0 when read, write operations have no effect.
1:0
PowerState—R/W. This field indicates the current power state of the IGD and can be used to set the
IGD into a new power state. If software attempts to write an unsupported state to this field, the write
operation must complete normally on the bus, but the data is discarded and no state change occurs.
00 = D0 (Default)
01 = D1 Not Supported– Writes will be blocked and will return the previous value.
10 = D2 Not Supported– Writes will be blocked and will return the previous value.
11 = D3