Datasheet

100 Intel

82845G/82845GL/82845GV GMCH Datasheet

3.5.3.17 INTRPIN—Interrupt Pin Register (Device 2)

Address Offset: 3Dh

Default Value: 01h

Access: RO

Size: 8 bits

3.5.3.18 MINGNT—Minimum Grant Register (Device 2)

Address Offset: 3Eh

Default Value: 00h

Access: RO

Size: 8 bits

3.5.3.19 MAXLAT—Maximum Latency Register (Device 2)

Address Offset: 3Fh

Default Value: 00h

Access: RO

Size: 8 bits

3.5.3.20 PMCAPID—Power Management Capabilities ID Register (Device 2)

Address Offset: D0h−D1h

Default Value: 0001h

Access: RO

Size: 16 bits

Bit Description

7:0

Interrupt Pin. As a single function device, the IGD specifies INTA# as its interrupt pin.

01h=INTA#.

Bit Description

7:0

Minimum Grant Value. The IGD does not burst as a PCI compliant master.

Bits[7:0]=00h.

Bit Description

7:0

Maximum Latency Value. Bits[7:0]=00h. The IGD has no specific requirements for how often it

needs to access the PCI bus.

Bit Description

15:8

NEXT_PTR. This contains a pointer to next item in capabilities list. This is the final capability in the

list and must be set to 00h.

7:0

CAP_ID. SIG defines this ID is 01h for power management.