Intel® 845G/845GL/845GV Chipset Datasheet Intel® 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) October 2002 Document Number: 290746-002
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Contents 1 Introduction ...........................................................................................................13 1.1 1.2 1.3 1.4 2 Signal Description ..............................................................................................21 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3 Terminology ...................................................................................................13 Related Documents .....................................................
3.5.1 3.5.2 4 DRAM Controller/Host-Hub Interface Device Registers (Device 0) .. 48 3.5.1.1 VID—Vendor Identification Register (Device 0) ................ 50 3.5.1.2 DID—Device Identification Register (Device 0)................. 50 3.5.1.3 PCICMD—PCI Command Register (Device 0) ................. 51 3.5.1.4 PCISTS—PCI Status Register (Device 0) ......................... 52 3.5.1.5 RID—Revision Identification Register (Device 0) .............. 53 3.5.1.6 SUBC—Sub-Class Code Register (Device 0) .............
3.5.3 3.5.4 4 3.5.2.9 HDR1—Header Type Register (Device 1).........................83 3.5.2.10 PBUSN1—Primary Bus Number Register (Device 1) .......83 3.5.2.11 SBUSN1—Secondary Bus Number Register (Device 1)...84 3.5.2.12 SUBUSN1—Subordinate Bus Number Register (Device 1).. 84 3.5.2.13 SMLT1—Secondary Bus Master Latency Timer Register (Device 1).............................................................................84 3.5.2.14 IOBASE1—I/O Base Address Register (Device 1)............85 3.5.2.
4.2 4.3 4.4 4.5 4.6 4.7 6 4.1.1 PSB Dynamic Bus Inversion........................................................... 105 4.1.2 System Bus Interrupt Delivery ........................................................ 106 4.1.3 Upstream Interrupt Messages......................................................... 106 System Memory Controller .......................................................................... 107 4.2.1 DDR SDRAM Interface Overview ...................................................
5 System Address ................................................................................................139 5.1 6 Electrical Characteristics ..............................................................................147 6.1 6.2 6.3 6.4 6.5 6.6 7 Intel® 82845G GMCH Ballout ......................................................................155 Package Information ....................................................................................170 Testability............................
Figures 1-1 2-1 2-2 2-3 3-1 3-2 3-3 3-4 4-1 4-2 5-1 5-2 6-1 7-1 7-2 7-3 7-4 9-1 8 Intel® 845G Chipset System Block Diagram.................................................. 16 Intel® 82845G GMCH Interface Block Diagram............................................. 22 Intel® GMCH System Clock and Reset Requirements .................................. 38 Full and Warm Reset Waveforms ..................................................................
Tables 2-1 2-2 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 7-1 7-2 8-1 8-2 8-3 8-4 8-5 9-1 DDR-to-SDR Signal Mapping ........................................................................26 Voltage Levels and RCOMP for Various Interfaces.......................................37 DRAM Controller/Host-Hub Register Address Map (Device 0)......................48 PAM Register Attributes.................................................................
Revision History Revision 10 Changes Date -001 Initial release May 2002 -002 Added 82845GV information (see appendix A for details) October 2002 Intel® 82845G/82845GL/82845GV GMCH Datasheet
Intel® 82845G GMCH Features Host Interface Support • One processor in a mPGA478 package • Hyper-Threading Technology support • 400/533 MHz PSB (100/133 MHz bus clock) • PSB Dynamic Bus Inversion on the data bus • 32-bit addressing for access to 4 GB of memory space • 8 deep In Order Queue • AGTL+ On-die Termination ■ System Memory Controller (SDR and DDR) — One, 64-bit wide SDR or DDR SDRAM data channel — Bandwidth up to 1 GB/s (SDR), and 2.
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Introduction 1 Introduction This Graphics and Memory Controller Hub (GMCH) datasheet is for the Intel® 82845G GMCH, Intel® 82845GL GMCH, and Intel® 82845GV GMCH. The 82845G GMCH is part of the Intel® 845G chipset, the 82845GL GMCH is part of the Intel® 845GL chipset, and the 82845GV GMCH is part of the Intel® 845GV chipset. Each chipset contains two main components: Graphics and Memory Controller Hub (GMCH) for the host bridge and I/O Controller Hub for the I/O subsystem.
Introduction Term Graphics Core The internal graphics related logic in the GMCH. Also known as the Integrated Graphics Device (IGD). HI Hub Interface. The proprietary hub interconnect that ties the GMCH to the ICH4. In this document HI cycles originating from or destined for the primary PCI interface on the ICH4 are generally referred to as HI/PCI or simply HI cycles. Host ® 1.2 Description This term is used synonymously with processor or CPU.
Introduction 1.3 Intel® 845G Chipset System Overview Figure 1-1 shows an example block diagram of an 845G chipset-based platform. The 845G chipset is designed for use in a desktop system based on an Intel® Pentium® 4 processor in a 478-pin package. The 845G chipset supports the Pentium 4 processor with 256-KB L2 cache and the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process. The processor interface supports the Pentium 4 processor subset of the Extended Mode of the Scalable Bus Protocol.
Introduction Figure 1-1. Intel® 845G Chipset System Block Diagram Processor VGA AGP 4x 1.06 GB/s Or 2 Intel® DVO Ports System Bus 400/533 MHz 845G Chipset Intel® 82845G Graphics and Memory Controller Hub (GMCH) System Memory Interface DDRSDRAM 1.6 / 2.1 GB/s Or PCI133 SDRAM 1.06 GB/s Hub Interface 4 IDE Devices PCI Slots UltraATA/100 PCI Bus 6 USB Ports, 3UHCI, EHCI AC '97 Codec(s) (optional) AC'97 2.
Introduction 1.4 Intel® 82845G GMCH Overview The GMCH provides the processor interface, SDRAM interface, AGP interface, hub interface, and integrated graphics with several display interfaces. 1.4.1 Host Interface The GMCH supports a single mPGA 478 processor with PSB frequencies of 400 MHz (100 MHz HCLK) / 533 MHz (133 MHz HCLK) and it also supports Hyper-Threading Technology. The GMCH uses a scalable PSB VTT between 1.15 V and 1.75 V and on-die termination.
Introduction 1.4.4 Multiplexed AGP and Intel® DVO Port Interface The GMCH multiplexes an AGP interface with two DVO ports. When an external AGP device is installed in the system, the IGD functionality is disabled. AGP Interface A single AGP or PCI-66 component or connector (not both) is supported by the GMCH’s AGP interface. Support for a single PCI-66 device is limited to the subset supported by the Accelerated Graphics Port Interface Specification, Revision 2.0. The AGP/PCI_B buffers operate only in 1.
Introduction The graphics features on the GMCH include: • 3D Setup and Render Engine — Discrete Triangles, Strips and Fans Support — Indexed Vertex and Flexible Vertex Formats — Pixel Accurate Fast Scissoring and Clipping Operation — Backface Culling Support — Supports D3D and OGL Pixelization Rules — Anti-Aliased Lines Support — Sprite Points Support • High Quality Texture Engine — Per Pixel Perspective Corrected Texture Mapping — Single Pass Texture Compositing (MultiTextures) at rate — 12 Levels of Deta
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Signal Description Signal Description 2 This section provides a detailed description of GMCH signals. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when at the high voltage level.
Signal Description Figure 2-1.
Signal Description 2.1 Host Interface Signals Signal Name Type Description ADS# I/O AGTL+ Address Strobe: The processor bus owner asserts ADS# to indicate the first of two cycles of a request phase. BNR# I/O AGTL+ Block Next Request: This signal is used to block the current request bus owner from issuing a new requests. This signal is used to dynamically control the processor bus pipeline depth. BPRI# O AGTL+ Priority Agent Bus Request: The GMCH is the only Priority Agent on the processor bus.
Signal Description Signal Name Type Description HDSTB_P[3:0]# I/O AGTL+ Differential Host Data Strobes: HDSTB_P[3:0]# and HDSTB_N[3:0]# are the differential source synchronous strobes used to transfer HD_[63:0]# and DINV_[3:0]# at the 4X transfer rate.
Signal Description 2.2 Memory Interface 2.2.1 DDR SDRAM Interface Signal Name Type Description SCMDCLK_[5:0] O SSTL_2 Differential DDR Clock: SCMDCLK and SCMDCLK# pairs are differential clock outputs. The crossing of the positive edge of SCMDCLK and the negative edge of SCMDCLK# is used to sample the address and control signals on the SDRAM. There are 3 pairs to each DIMM. SCMDCLK_[5:0]# O SSTL_2 Complementary Differential DDR Clock: These are the complementary Differential DDR Clock signals.
Signal Description 2.2.2 SDR SDRAM Interface The SDR interface signals are multiplexed with the DDR signals. At power up the functional strap setting on MEMSEL determines whether the memory interface is set up for DDR or SDR. The DDR-to-SDR signal mapping is provided in Table 2-1. Signal Name Type Description SCK_[7:0] O LVTTL SDR System Memory Clock: These signals provide the 133 MHz SDRAM clocks for the DIMMs. Note that there are two SCK per SDRAM row.
Signal Description Table 2-1.
Signal Description Table 2-1. DDR-to-SDR Signal Mapping (Sheet 3 of 3) 2.
Signal Description 2.4 AGP Interface Signals 2.4.1 AGP Addressing Signals Signal Name GPIPE# Type I AGP Description Pipelined Read: This signal is asserted by the current master to indicate a full width address is to be queued by the target. The master queues one request each rising clock edge while GPIPE# is asserted. When GPIPE# is deasserted, no new requests are queued across the GAD bus. GPIPE# is a sustained tri-state signal from the master (graphics controller) and is an input to the GMCH.
Signal Description 2.4.3 AGP Status Signals Signal Name Type Description O Status: GST_[2:0] provide information from the arbiter to an AGP Master on what it may do. GST_[2:0] only have meaning to the master when its GGNT# is asserted. When GGNT# is deasserted, these signals have no meaning and must be ignored. GST_[2:0] are always an output from the GMCH and an input to the master.
Signal Description 2.4.5 PCI Signals–AGP Semantics PCI signals are redefined when used in AGP transactions carried using AGP protocol extension. For transactions on the AGP interface carried using PCI protocol, these signals completely preserve PCI Local Bus Specification, Revision 2.1 semantics. The exact roles of all PCI signals during AGP transactions are defined below. Signal Name Type Description I/O s/t/s AGP Frame: GFRAME# is an output from the GMCH during Fast Writes.
Signal Description 2.4.6 PCI Pins during PCI Transactions on AGP Interface The PCI signals described in Section 2.4.5 behave according to PCI Local Bus Specification, Revision 2.1, when used to perform PCI transactions on the AGP Interface. 2.5 Multiplexed Intel® DVO Device Signal Interfaces The DVO signals, described in the following table, are multiplexed with the AGP signals.
Signal Description Name DVOBC_INTR# DVOC_FLDSTL Type Description I AGP DVOBC Interrupt: This signal may be used as an interrupt input for either of the multiplexed DVO devices. I AGP TV Field and Flat Panel Stall Signal: This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel. When used as a Field input, it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source.
Signal Description 2.5.1 Intel® DVO Signal Name to AGP Signal Name Pin Mapping The 82845G GMCH multiplexes an ADD_Detect signal with the G_PAR signal on the AGP bus. This signal acts as a strap and indicates whether the interface is in AGP or DVO mode (See ADD_DETECT signal description for further information). GSBA(7:0) act as straps for an ADD_ID. When an ADD card is present, ADD_DETECT=0 (DVO mode).
Signal Description 2.6 Analog Display Signal Name Type Description HSYNC O 3.3 V GPIO CRT Horizontal Synchronization: This signal is used as the horizontal sync (polarity is programmable) or “sync interval”. VSYNC O 3.3 V GPIO CRT Vertical Synchronization: This signal is used as the vertical sync (polarity is programmable). RED O Analog RED Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.
Signal Description 2.7 Clocks, Reset, and Miscellaneous Signals Signal Name 2.8 Type Description HCLKP HCLKN I CMOS Differential Host Clock In: These pins receive a low voltage differential host clock from the external clock synthesizer. GCLKIN I LVTTL 66 MHz Clock In: This pin receives a 66 MHz clock from the clock synthesizer. This clock is used by AGP and hub interface clock domains.
Signal Description Table 2-2 shows the VTT/VDD, VREF, RCOMP, and VSWING levels for the various interfaces. Table 2-2. Voltage Levels and RCOMP for Various Interfaces VTT/VDD (Volts) Interface Core VREF (volts) RCOMP (Ω) RCOMP term Vswing (Volts) 1.5 V NA NA NA 1.15 -1.75 V(1) 2/3 * VTT 25 1/3*VTT AGP/DVO 1.5 V 0.5 * VDD 40 HI1.5 1.5 V 0.35 69 1.25/2.5 V 0.5 * VDD 60 NA 3.3 V 0.5 * VDD 20 NA AGTL+ DDR - SSTL_2 SDR - LVTTL Note 2 NA 0.7 NOTE: 1.
Signal Description 2.10 Functional Straps Signal Name PSBSEL MEMSEL 2.11 Type Description I PSB Frequency Select: The PSBSEL is tied to the external BSEL resistor-divider circuitry. The value of the PSBSEL pin reflects the PSB frequency. The PSB runs at 400 MHz when PSBSEL is a 0 and runs at 533 MHz when PSBSEL is a 1. I Memory Configuration Select: This pin selects the SDR or DDR board configuration. The pin should be unconnected for DDR configuration.
Signal Description 2.12 Reset States 2.12.1 Full and Warm Reset States Figure 2-3. Full and Warm Reset Waveforms ICH4 Power ICH4 PWROK In 1 ms min ICH4 PCIRST# Out GMCH RSTIN# In Write on CF9h 1 ms min 1 ms min 1 ms min GMCH CPURST# Out GMCH Power GMCH PWROK In GMCH Reset State Unknown Full Reset Warm Reset Running Warm Reset Running All register bits assume their default values during full reset. A full reset occurs when PCIRST# (GMCH RSTIN#) is asserted and PWROK is deasserted.
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Register Description 3 Register Description This chapter describes the platform device PCI configuration structure and register accesses mechanisms. The chapter also provides a detailed description of the GMCH PCI configuration registers including bit/field descriptions.
Register Description Term 3.2 Description Reserved Bits Some of the GMCH registers described in this chapter contain reserved bits. These bits are labeled Reserved (Rsvd). Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved.
Register Description Logically, the ICH4 appears as multiple PCI devices within a single physical component also residing on PCI bus #0. One of the ICH4 devices is a PCI-to-PCI bridge. Logically, the primary side of the bridge resides on PCI #0 while the secondary side is the standard PCI expansion bus. Note: A physical PCI bus #0 does not exist and that the hub interface and the internal devices in the GMCH and ICH4 logically constitute PCI Bus #0 to configuration software. Figure 3-1.
Register Description 3.3.1 Standard PCI Bus Configuration Mechanism The PCI Local Bus Specification, Revision 2.1 defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Local Bus Specification, Revision 2.1 defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor.
Register Description have a Bus Number that matches the Secondary Bus Number of the GMCH’s “virtual” Host-toPCI_B/AGP bridge will be translated into Type 0 configuration cycles on the PCI_B/AGP interface. The GMCH will decode the Device Number field [15:11] and assert the appropriate GAD signal as an IDSEL in accordance with the PCI-to-PCI Bridge Type 0 configuration mechanism. The remaining address bits will be mapped as described in Figure 3-2. Figure 3-2.
Register Description Figure 3-3. Configuration Mechanism Type 1 Configuration Address to PCI Address Mapping CONFIG_ADDRESS 24 23 8 7 2 1 0 16 15 11 10 31 30 1 Reserved Bus Number Device Number Function Number Reg. Index X X PCI Address AD[31:0] 0 31 Bus Number Device Number 24 23 16 15 Function Number 11 10 87 Reg. Index 0 1 2 1 0 To prepare for mapping of the configuration cycles on AGP/PCI_B, the initialization software will go through the following sequence: 1.
Register Description Bit Description Configuration Enable (CFGE). 31 1 = Enable. 0 = Disable. 30:24 Reserved. These bits are read only and have a value of 0. Bus Number. When the Bus Number is programmed to 00h the target of the Configuration Cycle is a hub interface agent (GMCH, Intel® ICH4, etc.). The Configuration Cycle is forwarded to the hub interface if the Bus Number is programmed to 00h and the GMCH is not the target.
Register Description 3.5 Intel® GMCH Internal Device Registers 3.5.1 DRAM Controller/Host-Hub Interface Device Registers (Device 0) The DRAM controller and host-hub interface registers are in Device 0. This section contains the PCI configuration registers listed in order of ascending offset address. Table 3-1 provides the register address map for this device. Table 3-1.
Register Description Table 3-1.
Register Description 3.5.1.1 VID—Vendor Identification Register (Device 0) Address Offset: Default Value: Access: Size: 00–01h 8086h RO 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit 15:0 3.5.1.2 Description Vendor Identification (VID). This register field contains the PCI standard identification for Intel, 8086h.
Register Description 3.5.1.3 PCICMD—PCI Command Register (Device 0) Address Offset: Default Value: Access: Size: 04–05h 0006h RO, R/W 16 bits Since GMCH Device 0 does not physically reside on PCI_A, many of the bits are not implemented. Bit 15:10 9 Description Reserved. Fast Back-to-Back Enable (FB2B)—RO. Hardwired to 0. This bit controls whether or not the master can do fast back-to-back write. Since Device 0 is strictly a target, this bit is not implemented. SERR Enable (SERRE)—R/W.
Register Description 3.5.1.4 PCISTS—PCI Status Register (Device 0) Address Offset: Default Value: Access: Size: 06–07h 0090h RO, R/WC 16 bits PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI interface. Bit 14 is read/write clear. All other bits are Read Only. Since GMCH Device 0 does not physically reside on PCI_A, many of the bits are not implemented. Bit 15 Description Detected Parity Error (DPE)—RO. Hardwired to 0. Not implemented.
Register Description 3.5.1.5 RID—Revision Identification Register (Device 0) Address Offset: Default Value: Access: Size: 08h See table below RO 8 bits This register contains the revision number of the GMCH Device 0. Bit Description Revision Identification Number (RID). This is an 8-bit value that indicates the revision identification number for the GMCH Device 0. 82845G and 82845GL GMCH 7:0 01h = A1 Stepping 03h = B1 Stepping 82845GV GMCH 01h = A1 Stepping 3.5.1.
Register Description 3.5.1.8 MLT—Master Latency Timer Register (Device 0) Address Offset: Default Value: Access: Size: 0Dh 00h RO 8 bits Device 0 in the GMCH is not a PCI master. Therefore this register is not implemented. Bit 7:0 3.5.1.9 Description Reserved. HDR—Header Type Register (Device 0) Address Offset: Default Value: Access: Size: 0Eh 00h RO 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location.
Register Description 3.5.1.10 APBASE—Aperture Base Configuration Register (Device 0) Address Offset: Default Value: Access: Size: 10–13h 00000008h RO, R/W 32 bits The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics Aperture. The standard PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to 0 or behave as hardwired to 0).
Register Description 3.5.1.11 SVID—Subsystem Vendor Identification Register (Device 0) Address Offset: Default Value: Access: Size: 2C–2Dh 0000h R/W-Once 16 bits This value is used to identify the vendor of the subsystem. Bit 15:0 3.5.1.12 Description Subsystem Vendor ID (SUBVID)—R/WO. This field should be programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes read only.
Register Description 3.5.1.14 AGPM—AGP Miscellaneous Configuration Register (Device 0) Address Offset: Default Value: Access: Size: 51h 00h R/W 8 bits Bit 7:2 1 Description Reserved. Aperture Access Global Enable (APEN). This bit is used to prevent access to the graphics aperture from any port (CPU, HI, or AGP/PCI_B) before the aperture range is established by the configuration software and the appropriate translation table in the main SDRAM has been initialized. 0 = Disable. (Default).
Register Description 3.5.1.15 GC—Graphics Control Register (Device 0) Address Offset: Default Value: Access: Size: 52h 0000_1000b R/W 8 bits Bit 7 Description Reserved. Default = 0 Graphics Mode Select (GMS)—R/W. This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes. These 3 bits are valid only when Internal graphics is enabled. 000 = No memory pre-allocated. Default 001 = Reserved.
Register Description Notes on Pre-Allocated Memory for Graphics These Register Bits control the allocation of memory from main memory space for use as graphics local memory. The memory for TSEG is pre-allocated first and then the graphics local memory is pre-allocated. An example of this allocation mechanism is: TOM equals 64 MB, TSEG selected as 512 KB in size, Graphics Local Memory selected as 1 MB in size General System RAM available in system = 62.
Register Description 3.5.1.16 DRB[0:3]—DRAM Row Boundary Register (Device 0) Address Offset: Default Value: Access: Size: 60–63h (64h–6Fh Reserved) 01h Read/Write 8 bits The DRAM Row Boundary Register defines the upper boundary address of each DRAM row with a granularity of 32 MB. Each row has its own single-byte DRB register. For example, a value of 1 in DRB0 indicates that 32 MB of DRAM has been populated in the first row. Since the GMCH supports a total of four rows of memory, only DRB[0:3] are used.
Register Description 3.5.1.17 DRA—DRAM Row Attribute Register (Device 0) Address Offset: Default Value: Access: Size: 70–71h (72–77h Reserved) 00h R/W 8 bits The DRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of rows.
Register Description 3.5.1.18 DRT—DRAM Timing Register (Device 0) Address Offset: Default Value: Access: Size: 78–7Bh 00000000h Read/Write 32 bits This register controls the timing of the DRAM controller. Bit 31:18 Description Intel Reserved. DRAM Idle Timer. This field determines the number of clocks the SDRAM controller will remain in the idle state before it begins pre-charging all pages.
Register Description 3.5.1.19 DRC—DRAM Controller Mode Register (Device 0) Address Offset: Default Value: Access: Size: 7C–7Fh 00000000h R/W, RO 32 bits Bit 31:30 29 Description Revision Number (REV)—RO. This field reflects the revision number of the format used for SDR/ DDR register definition. Currently, this field must be 00, since this (rev “00”) is the only existing version of the specification. Initialization Complete (IC)—R/W.
Register Description Bit Description 3:1 Intel Reserved. DRAM Type (DT)—RO. This bit indicates SDRAM type. 0 3.5.1.20 0 = Single Data Rate (SDR) SDRAM 1 = Double Data Rate (DDR) SDRAM PAM[0:6]—Programmable Attribute Map Registers (Device 0) Address Offset: Default Value: Attribute: Size: 90–96h 00h R/W, RO 8 bits The GMCH allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 768-KB to 1-MB address range.
Register Description At the time that a hub interface or AGP accesses to the PAM region may occur, the targeted PAM segment must be programmed to be both readable and writeable. As an example, consider BIOS that is implemented on the expansion bus. During the initialization process, the BIOS can be shadowed in main memory to increase the system performance. When BIOS is shadowed in main memory, it should be copied to the same address location.
Register Description Microsoft MS-DOS* Application Area (00000h–9FFFh) The MS-DOS* area is 640 KB in size and it is further divided into two parts. The 512-KB area at 0 to 7FFFFh is always mapped to the main memory controlled by the GMCH, while the 128-KB address range from 080000h to 09FFFFh can be mapped to PCI_A or to main DRAM. By default this range is mapped to main memory and can be declared as a main memory hole (accesses forwarded to PCI_A) via the GMCH FDHC configuration register.
Register Description 3.5.1.21 FDHC—Fixed SDRAM Hole Control Register (Device 0) Address Offset: Default Value: Access: Size: 97h 00h R/W, RO 8 bits This 8-bit register controls a fixed SDRAM hole from 15 MB–16 MB. Bit 7 Description Hole Enable (HEN). This field enables a memory hole in SDRAM space. The SDRAM that lies “behind” this space is not remapped. 0 = No memory hole 1 = Memory hole from 15 MB to 16 MB. 6:0 3.5.1.22 Reserved.
Register Description 3.5.1.23 ESMRAMC—Extended System Management RAM Control Register (Device 0) Address Offset: Default Value: Access: Size: 9Eh 38h R/W, R/WC, RO, L 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MB. Note: When Extended SMRAM is used, the maximum amount of SDRAM accessible is limited to 256 MB.
Register Description 3.5.1.24 ACAPID—AGP Capability Identifier Register (Device 0) Address Offset: Default Value: Access: Size: A0–A3h 00200002h RO 32 bits This register provides standard identifier for AGP capability. Bit 3.5.1.25 Description 31:24 Reserved. 23:20 Major AGP Revision Number (MAJREV). These bits provide a major revision number of Accelerated Graphics Port interface Specification, Revision 2.0 to which this version of GMCH conforms. This field is hardwired to value of 0010b (i.e.
Register Description 3.5.1.26 AGPCMD—AGP Command Register (Device 0) Address Offset: Default Value: Access: Size: A8–ABh 00000000h RO, R/W 32 bits This register provides control of the AGP operational parameters. Bit 31:10 Description Intel Reserved. SideBand Addressing Enable (SBAEN). 9 0 = Disable. 1 = Enable. 8 7:5 AGP Enable (AGPEN). When this bit is reset to 0, the GMCH will ignore all AGP operations, including the sync cycle.
Register Description 3.5.1.28 APSIZE—Aperture Size Register (Device 0) Address Offset: Default Value: Access: Size: B4h 00h RO, R/W 8 bits This register determines the effective size of the Graphics Aperture used for a particular GMCH configuration. This register can be updated by the GMCH-specific BIOS configuration sequence before the PCI standard bus enumeration sequence takes place. If the register is not updated then a default value will select an aperture of maximum size (i.e., 256 MB).
Register Description 3.5.1.30 AMTT—AGP MTT Control Register (Device 0) Address Offset: Default Value: Access: Size: BCh 10h Read Only, Read/Write 8 bits AMTT is an 8-bit register that controls the amount of time that the GMCH’s arbiter allows AGP/ PCI master to perform multiple back-to-back transactions.
Register Description 3.5.1.32 GMCHCFG—GMCH Configuration Register (Device 0) Address Offset: Default Value: Access: Size: C6–C7h 0C01h R/W, RO 16 bits Bit 15:13 12 Description Intel Reserved. Core/PSB Frequency Select (PSBFREQ)—RO. The default value of this bit is set by the strap assigned to pin PSBSEL and is latched at the rising edge of PWROK.
Register Description 3.5.1.33 ERRSTS—Error Status Register (Device 0) Address Offset: Default Value: Access: Size: C8–C9h 0000h R/WC 16 bits This register is used to report various error conditions via the SERR HI messaging mechanism. An SERR HI message is generated on a zero to one transition of any of these flags (if enabled by the ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated.
Register Description 3.5.1.34 ERRCMD—Error Command Register (Device 0) Address Offset: Default Value: Access: Size: CA–CBh 0000h RO, R/W 16 bits This register controls the GMCH responses to various system errors. Since the GMCH does not have an SERR# signal, SERR messages are passed from the GMCH to the ICH over HI. When a bit in this register is set, a SERR message will be generated on HI whenever the corresponding flag is set in the ERRSTS register.
Register Description 3.5.1.35 SMICMD—SMI Command Register (Device 0) Address Offset: Default Value: Access: Size: CC–CDh 0000h RO, R/W 16 bits This register enables various errors to generate a SMI message via the hub interface. Bit 15:0 3.5.1.36 Description Intel Reserved. SCICMD—SCI Command Register (Device 0) Address Offset: Default Value: Access: Size: CE–CDh 0000h RO, R/W 16 bits This register enables various errors to generate a SMI message via the hub interface. Bit 15:0 3.5.1.
Register Description 3.5.1.38 CAPREG—Capability Identification Register (Device 0) Address Offset: Default: Access: Size E4h–E8h 0x_x105_A009h RO 40 bits Bit Description Part Identifier. 0E1h = 82845GL 39:28 0B1h = 82845GV 000h = 82845G with Revision ID of 01h 030h = 82845G with Revision ID of 03h 27:24 CAPREG Version. This field has the value 0001b to identify the first revision of the CAPREG definition. 23:16 Cap_length. This field has the value 05h indicating the structure length.
Register Description 3.5.2 Host-to-AGP Bridge Registers (Device 1) The host-to-AGP Bridge (virtual PCI-to-PCI) registers are in Device 1. This section contains the PCI configuration registers listed in order of ascending offset address. Table 3-3 provides the register address map for this device. Table 3-3.
Register Description 3.5.2.1 VID1—Vendor Identification Register (Device 1) Address Offset: Default Value: Access: Size: 00–01h 8086h RO 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. 3.5.2.2 Bit Description 15:0 Vendor Identification Device 1 (VID1). This register field contains the PCI standard identification for Intel, 8086h.
Register Description 3.5.2.3 PCICMD1—PCI Command Register (Device 1) Address Offset: Default Value: Access: Size: 04–05h 0000h RO, R/W 16 bits Bit 15:10 Description Reserved. 9 Fast Back-to-Back Enable (FB2B)—RO. Hardwired to 0. 8 SERR Message Enable (SERRE). This bit is a global enable bit for Device 1 SERR messaging. The GMCH communicates the SERR# condition by sending an SERR message to the ICH.
Register Description 3.5.2.4 PCISTS1—PCI Status Register (Device 1) Address Offset: Default Value: Access: Size: 06–07h 00A0h RO, R/WC 16 bits PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the “virtual” PCI-to-PCI bridge embedded within the GMCH. Bit 15 Description Detected Parity Error (DPE)—RO. Hardwired to 0. Parity is not supported on the primary side of this device. Signaled System Error (SSE)—R/WC.
Register Description 3.5.2.5 RID1—Revision Identification Register (Device 1) Address Offset: Default Value: Access: Size: 08h see table below RO 8 bits This register contains the revision number of the GMCH Device 1. Bit Description Revision Identification Number (RID). This is an 8-bit value that indicates the revision identification number for the GMCH Device 1. 82845G and 82845GL GMCH 7:0 01h = A1 Stepping 03h = B1 Stepping 82845GV GMCH 01h = A1 Stepping 3.5.2.
Register Description 3.5.2.8 MLT1—Master Latency Timer Register (Device 1) Address Offset: Default Value: Access: Size: 0Dh 00h RO, R/W 8 bits This functionality is not applicable. It is described here since these bits should be implemented as a read/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.” 3.5.2.9 Bit Description 7:3 Scratchpad MLT (NA7.3).
Register Description 3.5.2.11 SBUSN1—Secondary Bus Number Register (Device 1) Address Offset: Default Value: Access: Size: 19h 00h R/W 8 bits This register identifies the bus number assigned to the second bus side of the “virtual” PCI-to-PCI bridge (i.e., to PCI_B/AGP). This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI_B/AGP. Bit 7:0 3.5.2.12 Description Secondary Bus Number (BUSN).
Register Description 3.5.2.14 IOBASE1—I/O Base Address Register (Device 1) Address Offset: Default Value: Access: Size: 1Ch F0h RO, R/W 8 bits This register controls the processor to PCI_B/AGP I/O access routing based on the following formula: IO_BASE ≤ address ≤ IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB boundary. Bit 3.5.2.
Register Description 3.5.2.16 SSTS1—Secondary Status Register (Device 1) Address Offset: Default Value: Access: Size: 1Eh 02A0h RO, R/WC 16 bits SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., PCI_B/AGP side) of the “virtual” PCI-to-PCI bridge embedded within the GMCH. Bit Description Detected Parity Error (DPE)—R/WC. 15 14 0 = Software sets DPE1 to 0 by writing a 1 to this bit.
Register Description 3.5.2.17 MBASE1—Memory Base Address Register (Device 1) Address Offset: Default Value: Access: Size: 20–21h FFF0h R/W 16 bits This register controls the processor to PCI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom four bits of this register are read only and return zeros when read.
Register Description 3.5.2.18 MLIMIT1—Memory Limit Address Register (Device 1) Address Offset: Default Value: Access: Size: 22–23h 0000h RO, R/W 16 bits This register controls the CPU to PCI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom four bits of this register are read-only and return zeros when read.
Register Description 3.5.2.19 PMBASE1—Prefetchable Memory Base Address Register (Device 1) Address Offset: Default Value: Access: Size: 24–25h FFF0h R/W 16 bits This register controls the processor to PCI_B prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address.
Register Description 3.5.2.21 BCTRL1—Bridge Control Register (Device 1) Address Offset: Default Value: Access: Size: 3Eh 00h RO, R/W 8 bits This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI bridges. The BCTRL1 provides additional control for the secondary interface (i.e., PCI_B/AGP) as well as some bits that affect the overall behavior of the “virtual” PCI-to-PCI bridge embedded within the GMCH (e.g., VGA compatible address ranges mapping).
Register Description The bit field definitions for VGAEN and MDAP are detailed in Table 3-4. Table 3-4. VGAEN and MDAP Bit Definitions 3.5.2.22 VGAEN MDAP Description 0 0 All References to MDA and VGA space are routed to hub interface. 0 1 Illegal combination 1 0 All VGA references are routed to this bus. MDA references are routed to the hub interface. 1 1 All VGA references are routed to this bus. MDA references are routed to hub interface.
Register Description 3.5.3 Integrated Graphics Device Registers (Device 2) The Integrated Graphics Device registers are in Device 2. This section contains the PCI configuration registers listed in order of ascending offset address. Table 3-5 provides the register address map for this device. Table 3-5.
Register Description 3.5.3.1 VID2—Vendor Identification Register (Device 2) Address Offset: Default Value: Access Attributes: Size: 00h−01h 8086h Read Only 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit 15:0 3.5.3.2 Description Vendor Identification Number. This is a 16-bit value assigned to Intel = 8086.
Register Description 3.5.3.3 PCICMD2—PCI Command Register (Device 2) Address Offset: Default: Access: Size: 04h−05h 0000h RO, R/W 16 bits This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory. Bit 15:10 Description Reserved. 9 Fast Back-to-Back (FB2B)—RO. Hardwired to 0. Not Implemented. 8 SERR# Enable (SERRE)—RO. Hardwired to 0. Not Implemented.
Register Description 3.5.3.4 PCISTS2—PCI Status Register (Device 2) Address Offset: Default Value: Access: Size: 06h−07h 0090h RO, R/WC 16 bits PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. Bit 15 Detected Parity Error (DPE)—RO. Hardwired to 0. IGD does not detect parity. 14 Signaled System Error (SSE)—RO. Hardwired to 0. The IGD never asserts SERR# 13 Received Master Abort Status (RMAS)—RO. Hardwired to 0.
Register Description 3.5.3.6 CC—Class Code Register (Device 2) Address Offset: Default Value: Access: Size: 09h−0Bh 030000h RO 24 bits This register contains the device programming interface information related to the Sub-Class Code and Base Class Code definition for the IGD. This register also contains the Base Class Code and the function sub-class in relation to the Base Class Code. Bit 23:16 Description Base Class Code (BASEC). 03=Display controller Sub-Class Code (SCC).
Register Description 3.5.3.9 HDR2—Header Type Register (Device 2) Address Offset: Default Value: Access: Size: 0Eh 00h RO 8 bits This register contains the Header Type of the IGD. Bit 7:0 3.5.3.10 Description Header Code (H). This is an 8-bit value that indicates the Header Code for the IGD. 00h = Single function device with a type 0 configuration space format.
Register Description 3.5.3.11 MMADR—Memory Mapped Range Address Register (Device 2) Address Offset: Default Value: Access: Size: 14– 17h 00000000h R/W, RO 32 bits This register requests allocation for the IGD registers and instruction ports. The allocation is for 512 KB and the base address is defined by bits [31:19]. Bit 31:19 Memory Base Address— R/W. Set by the operating system. These bits correspond to address signals [31:19]. 18:4 Address Mask— RO.
Register Description 3.5.3.14 ROMADR—Video BIOS ROM Base Address Registers (Device 2) Address Offset: Default Value: Access: Size: 30–33h 00000000h R/W, RO 32 bits The IGD does not use a separate BIOS ROM; therefore, this register is hardwired to zeros. Bit 31:18 ROM Base Address—RO. Hardwired to zeros. 17:11 Address Mask—RO. Hardwired to zeros to indicate 256-KB address range. 10:1 Reserved. Hardwired to zeros. 0 3.5.3.15 Description ROM BIOS Enable—RO.
Register Description 3.5.3.17 INTRPIN—Interrupt Pin Register (Device 2) Address Offset: Default Value: Access: Size: 3Dh 01h RO 8 bits Bit 7:0 3.5.3.18 Description Interrupt Pin. As a single function device, the IGD specifies INTA# as its interrupt pin. 01h=INTA#. MINGNT—Minimum Grant Register (Device 2) Address Offset: Default Value: Access: Size: 3Eh 00h RO 8 bits Bit 7:0 3.5.3.19 Description Minimum Grant Value. The IGD does not burst as a PCI compliant master. Bits[7:0]=00h.
Register Description 3.5.3.21 PMCAP—Power Management Capabilities Register (Device 2) Address Offset: Default Value: Access: Size: D2h−D3h 0021h RO 16 bits Bit 15:11 PME Support. Hardwired to 0. This field indicates the power states in which the IGD may assert PME#. The IGD does not assert the PME# signal. 10 D2. Hardwired to 0. The D2 power management state is not supported. 9 D1. Hardwired to 0. The D1 power management state is not supported. 8:6 Reserved. Read as zeros.
Register Description 3.5.4 Device 6 Registers Device 6 registers are Intel Reserved, except for the following two registers. 3.5.4.1 DWTC—DRAM Write Throttling Control Register (Device 6) Address Offset Default Value Access Size: D0–D7h 0000000000000000h R/W, L 64 bits Bits Description 63:41 Intel Reserved. 40:28 Global Write Hexword Threshold (GWHT).
Register Description 3.5.4.2 DRTC—DRAM Read Throttling Control Register (Device 6) Address Offset Default Value Access Size: D8h 0000000000000000h R/W, L 64 bits Bits Description 63:41 Intel Reserved. 40:28 Global Read Hexword Threshold (GRHT). The thirteen-bit value held in this field is multiplied by 2 15 to arrive at the number of hexwords that must be read within the Global DRAM Read Sampling Window in order to cause the throttling mechanism to be invoked. 27:22 Read Throttle Time (RTT).
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Functional Description 4 Functional Description This chapter describes the GMCH interfaces and functional units including the processor system bus interface, the AGP interface, system memory controller, integrated graphics device, DVO interfaces, display interfaces, power management, and clocking. 4.1 Processor System Bus The GMCH supports a single mPGA 478 processor with PSB frequencies of 400 MHz (100 MHz HCLK) / 533 MHz (133 MHz HCLK) and it also supports Hyper-Threading Technology.
Functional Description When the processor or the GMCH drives data, each 16-bit segment is analyzed. If more than 8 of the 16 signals would normally be driven low on the bus, the corresponding DINV# signal is asserted and the data is inverted prior to being driven on the bus. When the processor or the GMCH receives data, it monitors DINV[3:0]# to determine if the corresponding data segment should be inverted. 4.1.2 System Bus Interrupt Delivery Pentium 4 processors support system bus interrupt delivery.
Functional Description 4.2 System Memory Controller The GMCH can be configured to support either SDR SDRAM or DDR SDRAM memory. 4.2.1 DDR SDRAM Interface Overview The GMCH can support DDR266 and DDR200 in DDR mode with SSTL_2 signaling.
Functional Description 4.2.3 Memory Organization and Configuration In the following discussion the term “row” refers to a set of memory devices that are simultaneously selected by a chip select signal. The GMCH supports a maximum of 4 rows of memory. For the purposes of this discussion, a “side” of a DIMM is equivalent to a “row” of SDRAM devices.
Functional Description Memory Detection and Initialization Before any cycles to the memory interface can be supported, the GMCH SDRAM registers must be initialized. The GMCH must be configured for operation with the installed memory types. Detection of memory type and size is done via the System Management Bus (SMB) interface on the ICH4. This two-wire bus is used to extract the SDRAM type and size information from the Serial Presence Detect port on the SDRAM DIMMs.
Functional Description Addr BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 R/C/B Row/Page Size (Mbyet) Tech (Mbit) Configuration Table 4-5.
Functional Description 4.3 AGP Interface See the Accelerated Graphics Port Interface Specification, Revision 2.0 for additional details about the AGP interface. 4.3.1 Overview The GMCH multiplexes an AGP interface with two DVO ports. The DVO ports can support single channel DVO devices or can combine to support dual-channel devices, supporting higher resolutions and refresh rates. When an external AGP device is used, the multiplexed DVO ports are not available, as the GMCH’s IGD will be disabled.
Functional Description 4.3.1.2 AGP Target Operations As an initiator, the GMCH does not initiate cycles using AGP enhanced protocols. The GMCH supports AGP target interface to main memory only. The GMCH supports interleaved AGP and PCI transactions. The Table 4-6 summarizes target operation support of GMCH for AGP masters. Table 4-6.
Functional Description 4.3.1.3 AGP Transaction Ordering The GMCH observes transaction ordering rules as defined by the Accelerated Graphics Port Interface Specification, Revision 2.0. The GMCH implements read after write hazard protection for normal priority commands through the use of a “pseudo FENCE.” When a normal priority read command is placed in the command queue, it is checked for possible conflicts with any normal priority write commands that have been received but not yet delivered to SDRAM.
Functional Description 4.3.1.6 4X AGP Protocol In addition to the 1X and 2X AGP protocol, the GMCH supports 4X AGP read and write data transfers and 4X sideband address generation. The 4X operation is compliant with the 4X AGP specification as currently described in the Accelerated Graphics Port Interface Specification, Revision 2.0. The GMCH indicates that it supports 4X data transfers through RATE[2] (bit 2) of the AGP Status register.
Functional Description 4.3.2 PCI Semantic Transactions on AGP The GMCH accepts and generates PCI semantic transactions on the AGP bus. The GMCH guarantees that PCI semantic accesses to SDRAM are kept coherent with the processor caches by generating snoops to the processor bus. 4.3.2.1 GMCH Initiator and Target PCI Operations Table 4-7 summarizes PCI target operation support of the GMCH for AGP/PCI_B bus initiators. The cycles can be either destined to main memory or the hub interface bus. Table 4-7.
Functional Description Memory Read Line, and Memory Read Multiple: These commands are treated identically by the GMCH. The GMCH issues two snoops (a snoop followed by a snoop-ahead) on the host bus and releases the processor bus for other traffic. When the first DWord of the first cache line is delivered and GFRAME# is still asserted, the GMCH issues another snoop-ahead on the host bus. This allows the GMCH to continuously supply data during memory read line and memory read multiple bursts.
Functional Description Table 4-8. PCI Commands Supported by GMCH When Acting As an AGP/PCI_B Initiator (Sheet 2 of 2) Source Bus Command Other Encoded Information GMCH Host Bridge Corresponding PCI_B Command GC/BE[3:0]# Encoding None N/A Memory Write 0111 Source Bus: Host EA Memory Access Address ≥ 4 GB Source Bus: Hub Interface Memory Write - NOTES: 1. Processor to AGP/PCI_B bus can result in deadlocks. Locked access to AGP/PCI_B bus is strongly discouraged. 2.
Functional Description Reads • Read cycle is immediately retried (the GMCH retries the read cycle in three PCI clocks from GFRAME# driven active) due to a pending processor-AGP or hub interface-AGP write transaction. It is further handled using the Delayed Transaction mechanism described in a later section. This can occur as a result of the processor posting memory write cycles to the AGP or the GMCH storing a processor to AGP write cycle in the deferred queue.
Functional Description 4.4 Integrated Graphics Device (IGD) The GMCH provides a highly integrated graphics accelerator while allowing a flexible integrated system graphics solution (see Figure 4-1). Figure 4-1. Intel® GMCH Graphics Block Diagram Video Engine VGA DAC 2D Engine Instr.
Functional Description The entire IGD is fed with data from the memory controller. The performance of the IGD is directly related to the amount of bandwidth available. If the engines are not receiving data fast enough from the memory controller (e.g., PC133), the rest of the IGD will also be affected. The rest of this section focuses on explaining the IGD components and dependencies. 4.4.
Functional Description Zone Rendering Zone Rendering Technology is a unique mechanism that addresses memory bandwidth limitations by reducing the required memory bandwidth for graphics. The 3D graphics engine divides the frame buffer into rectangular zones and then sorts the triangles into memory by zone. The 3D graphics engine then completely processes the zone, writing the pixel data to memory and then proceeds to the next zone.
Functional Description Perspective Correct Texture Support A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon. A texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in perspective, it is important that texture be mapped in perspective as well. Texture Formats and Storage The GMCH supports up to 32 bits of color for non-palettized textures.
Functional Description GMCH supports 7 types of texture filtering: • Nearest (aka Point Filtering): Texel with coordinates nearest to the desired pixel is used. (This is used if only one LOD is present). • Linear (aka Bilinear Filtering): A weighted average of a 2x2 area of texels surrounding the desired pixel are used. (This is used if only one LOD is present). • Nearest MIP Nearest (aka Point Filtering): This is used if many LODs are present.
Functional Description 4.4.1.5 Raster Engine The Raster Engine is where the color data (e.g., fogging, specular RGB, texture map blending, etc.) is processed. The final color of the pixel is calculated and the RGBA value combined with the corresponding components resulting from the Texture Engine. These textured pixels are modified by the specular and fog parameters. These specular highlighted, fogged, textured pixels are color blended with the existing values in the frame buffer.
Functional Description Vertex and Per Pixel Fogging Fogging is used to create atmospheric effects (e.g., low visibility conditions) in flight simulatortype games. It adds another level of realism to computer-generated scenes. Fog can be used for depth cueing or hiding distant objects. With fog, distant objects can be rendered with fewer details (less polygons), thereby improving the rendering speed or frame rate.
Functional Description Depth Buffer The Raster Engine can read and write from this buffer and use the data in per fragment operations that determine whether resultant color and depth value of the pixel for the fragment are to be updated or not. Typical applications for entertainment or visual simulations with exterior scenes require far/near ratios of 1000 to 10000. At 1000, 98% of the range is spent on the first 2% of the depth.
Functional Description 4.4.1.7 GMCH VGA Registers The 2D registers are a combination of registers defined by IBM when the Video Graphics Array (VGA) was first introduced and others that Intel has added to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard. 4.4.1.8 Logical 128-Bit Fixed BLT and 256-Bit Fill Engine Using this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft Windows*.
Functional Description 4.4.2 Video Engine 4.4.2.1 Hardware Motion Compensation The Motion Compensation (MC) process consists of reconstructing a new picture by predicting (either forward, backward, or bidirectionally) the resulting pixel colors from one or more reference pictures. The GMCH receives the video stream and implements Motion Compensation and subsequent steps in hardware.
Functional Description 4.4.2.4 Overlay Plane The overlay engine provides a method of merging either video capture data (from an external Video Capture device) or data delivered by the processor, with the graphics data on the screen. The source data can be mirrored horizontally or vertically or both. Source/Destination Color Keying/Chromakeying Overlay source/destination chromakeying enables blending of the overlay with the underlying graphics background.
Functional Description Dynamic Bob and Weave Interlaced data that originates from a video camera creates two fields that are temporally offset by 1/60 of a second. There are several schemes to deinterlace the video stream: line replication, vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the previous field and inserts them into the current field to construct the frame – this is known as Weaving.
Functional Description 4.5 Display Interfaces The GMCH has three display ports, one analog and two digital. Each port can transmit data according to one or more protocols. The digital ports are connected to an external device that converts one protocol to another. Examples of this are TV encoders, external DACs, LVDS transmitters, and TMDS transmitters. Each display port has control signals that may be used to control, configure, and/or determine the capabilities of an external device.
Functional Description 4.5.1 Analog Display Port Characteristics The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The intended target device is for a CRT-based monitor with a VGA connector. Display devices such as LCD panels with analog inputs may work satisfactory but no functionality has been added to the signals to enhance that capability. Table 4-10.
Functional Description DDC (Display Data Channel) DDC is a standard defined by VESA. Its purpose is to allow communication between the host system and display. Both configuration and control information can be exchanged allowing plugand-play systems to be realized. Support for DDC 1 and 2 is implemented. The GMCH uses the DDCA_Clk and Data to communicate with the analog monitor. 4.5.2 Digital Display Interface The GMCH has several options for driving digital displays.
Functional Description TV-Out Capabilities While traditional TVs are not digital displays, the GMCH uses a digital display channel to communicate with a TV-Out transmitter. For that reason, the GMCH considers a TV-Output to be a digital display. The GMCH supports NTSC/PAL/SECAM standard definition formats. The GMCH generates the proper timing for the external encoder. The external encoder is responsible for generation of the proper format signal. Since the multiplexed DVO interface is 1.
Functional Description DDC (Display Data Channel) The multiplexed digital display interface uses the MDVI_CLK and MDVI_DATA signals to interrogate the panel. The GMCH supports the DDC2B protocol to initiate the transfer of EDID data. The multiplexed digital display interface uses the M_I2C bus to interrogate the external transmitter. Optional High Speed (Dual-Channel) Interface The multiplexed digital display ports can operate in a single 24-bit mode.
Functional Description 4.6 Power and Thermal Management 4.6.1 Power Management Support Overview • • • • 4.6.2 ACPI Supported System States: S0, S1(desktop), S3, S4, S5, C0, C1, C2 (desktop) Graphics States: D0, D3 Monitor States: D0, D1, D2, D3 Processor Power State Control • C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK# is deasserted and the processor core is active. The processor can service snoops and maintain cache coherency in this state.
Functional Description 4.6.5 Monitor State Control • • • • 4.7 D0 (On): In this state, both HSYNC and VSYNC are pulsed. D1 (Standby): The D1 monitor state is the standby mode. VSYNC is pulsed. D2 (Suspend): The D2 monitor state is the suspend mode. HSYNC is pulsed. D3 (Off): The D3 power state is the off mode. HSYNC and VSYNC are not pulsed in this state. Clocking Figure 4-2 shows a block diagram of an 845G chipset-based system.
Functional Description Figure 4-2.
System Address System Address 5 An mPGA478 processor system based on the GMCH supports 4 GB of addressable memory space and 64 KB+3 of addressable I/O space. There is a programmable memory address space under the 1-MB region that is divided into regions which can be individually controlled with programmable attributes (e.g., disable, read/write, write only, or read only). Attribute programming is described in Chapter 3.
System Address Figure 5-1. Memory System Address Map 4 GB Graphics Memory PCI Memory Address Range AGP Graphics Aperture Top of Main Memory Main Memory Address Range Independently Programmable Non-overlapping Windows Figure 5-2.
System Address 5.1.1 Compatibility Area This area is divided into the following address regions: • • • • • 0 – 640 KB DOS Area 640 – 768 KB Video Buffer Area 768 – 896 KB in 16-KB sections (total of 8 sections) - Expansion Area 896 – 960 KB in 16-KB sections (total of 4 sections) - Extended System BIOS Area 960 KB – 1 MB Memory (BIOS Area) - System BIOS Area There are fifteen memory segments in the compatibility area.
System Address Compatible SMRAM Address Range (A0000h–BFFFFh) When compatible SMM space is enabled, SMM-mode processor accesses to this range are routed to physical system SDRAM at this address. Non-SMM-mode processor accesses to this range are considered to be to the Video Buffer Area as described above. AGP and hub interface originated cycles to enabled SMM space are not allowed and are considered to be to the Video Buffer Area.
System Address 5.1.2 Extended Memory Area This memory area covers 100000h (1 MB) to FFFFFFFFh (4 GB–1 Byte) address range and it is divided into the following regions: • Main System SDRAM Memory from 1 MB to the Top of Memory; maximum of 2 GB SDRAM.
System Address Table 5-2 details the location and attributes of the regions. Enabling/disabling these ranges are described in the GMCH Control Register Device 0 (GC). Table 5-2. Pre-allocated Memory Memory Segments Attributes Comments 00000000h–03E7FFFFh R/W 03E80000h–03F7FFFFh R/W 03F80000h–03FFFFFFh SMM Mode Only - processor reads TSEG Address Range 03F80000h–03FFFFFFh SMM Mode Only - processor reads TSEG Pre-allocated Memory Available System Memory 62.5 MB Pre-allocated Graphics VGA memory.
System Address PCI Memory Address Range (Top of Main Memory to 4 GB) The address range from the top of main SDRAM to 4 GB (top of physical memory space supported by the GMCH) is normally mapped via the hub interface to PCI. As an internal graphics configuration, there are two exceptions to this rule: • Addresses decoded to graphics configuration registers. • Addresses decoded to the Memory Mapped Range of the Internal Graphics Device. Both exception cases are forwarded to the Internal Graphics Device.
System Address 5.1.3 AGP Memory Address Ranges The GMCH can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in the GMCH’s Device 1 configuration space. The first range is controlled via the Memory Base Register (MBASE) and Memory Limit Register (MLIMIT) registers. The second range is controlled via the Prefetchable Memory Base (PMBASE) and Prefetchable Memory Limit (PMLIMIT) registers.
Electrical Characteristics 6 Electrical Characteristics This chapter contains the thermal characteristics, power characteristics and DC characteristics for the GMCH component. Note: 6.1 SDR signals are multiplexed with DDR signals. The specific signal’s timing and voltage level is dependent on the 845G GMCH memory mode selected. This document differentiates the two by following each signal with either SDR or DDR, as appropriate.
Electrical Characteristics 6.3 Power Characteristics Table 6-3. Power Characteristics Symbol Parameter PGMCH(DDR) Thermal Design Power PGMCH(SDR) Thermal Design Power IVCC(DDR) 1.5 V Core Supply Current IVCC(SDR) IVCCAGP Max Unit W Notes 1 W 1 2.46 A 2 1.5 V Core Supply Current 2.0 A 2 1.5 V AGP Supply Current (AGP mode) 0.37 A 2 IVCCAGP 1.5 V AGP Supply Current (DVO mode) 0.18 A 2 IVCCHI 1.5 V Hub Interface Supply Current 90 mA 2 IVTTFSB GMCH VTT supply Current 2.
Electrical Characteristics Table 6-4.
Electrical Characteristics 6.5 DC Parameters Table 6-5. DC Operating Characteristics Signal Name Parameter Min Nom Max Unit I/O Buffer Supply Voltage VCC Core Voltage 1.425 1.5 1.575 V VCCAGP AGP I/O Voltage 1.425 1.5 1.575 V VCCHI Hub Interface I/O Voltage 1.425 1.5 1.575 V VCCA_DAC DAC Supply Voltage 1.425 1.5 1.575 V VTT Host AGTL+ Termination Voltage 1.15 N/A 1.75 V VCCSM(DDR) DDR I/O Supply Voltage 2.375 2.5 2.625 V VCCSM(SDR) SDR I/O Supply Voltage 3.
Electrical Characteristics Table 6-6. Symbol DC Characteristics (Sheet 1 of 2) Signal Group Parameter Min Nom Max Unit Notes 1.5 V AGP and Intel® DVO Interface: Functional Operating Range (VCC=1.5 V ± 5%) VIL_AGP (a,b,w) AGP/DVO Input Low Voltage –0.5 0.4VDDQ V VIH_AGP (a,b,w) AGP/DVO Input High Voltage 0.6VDDQ VDDQ+0.5 V VOL_AGP (a,c,x) AGP/DVO Output Low Voltage 0.15VDDQ V Iol = 1 mA VOH_AGP (a,c,x) AGP/DVO Output High Voltage V Ioh = -0.
Electrical Characteristics Table 6-6. Symbol DC Characteristics (Sheet 2 of 2) Signal Group Parameter Min Nom Max Unit SMVREF (SDR)–0.350 V Notes 3.3V SDR System Memory: Functional Operating Range (VCC=3.
Electrical Characteristics Figure 6-1. System Bus HCLKP/N VCROSS Range Vcross(rel) Max 550 Allowable Crossing Point (mV) 500 450 Vcross Range For VHigh > 0.71V 400 Vcross Range For VHigh < 0.71V 350 300 Vcross(rel) Min 250 200 625 650 675 700 725 750 775 800 825 850 VHigh Average (mV) (Measured) Vcross(rel) Max = 0.5 (Vhavg - 0.710) + .550 Vcross(rel) Min = 0.5 (Vhavg - 0.710) + .250 6.
Electrical Characteristics 6.6.2 DAC Reference and Output Specifications Table 6-8. DAC Reference and Output Specifications Parameter Min Typical Max Units Notes Reference resistor 137 Ω 1% tolerance, 1/16 W RED, GREEN, BLUE termination resistor 75 Ω Note 1, 1% tolerance, 1/16 W RED#,GREEN#,BLUE# termination resistor 37.
Ballout and Package Information Ballout and Package Information 7 This chapter provides the ballout listing and the package dimensions for the 82845G GMCH. Intel® 82845G GMCH Ballout 7.1 Figure 7-1 and Figure 7-2 show the 82845G GMCH footprint with the ball names listed for each ball. Table 7-1 lists the ballout organized by ball number. Table 7-2 lists the ballout organized alphabetically by signal name.
Ballout and Package Information Figure 7-1.
Ballout and Package Information Figure 7-2.
Ballout and Package Information Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # 158 Signal Name Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # Signal Name Table 7-1.
Ballout and Package Information Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # Signal Name Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # E2 GSBA_5 G2 E3 VSS E4 GSBA_4 E5 E7 Signal Name Table 7-1.
Ballout and Package Information Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # 160 Signal Name Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # Signal Name Table 7-1.
Ballout and Package Information Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # Signal Name Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # Signal Name Table 7-1.
Ballout and Package Information Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # 162 Signal Name Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # Signal Name Table 7-1.
Ballout and Package Information Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # Signal Name Table 7-1. Intel® 82845G GMCH Ballout by Ball Number Ball # AP16 SDQ_25 AR23 AP17 SMAA_7 AP18 SDQ_30 AP19 Signal Name Table 7-1.
Ballout and Package Information Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Signal Name 164 Ball # Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Signal Name Ball # Table 7-2.
Ballout and Package Information Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Signal Name HD_8# Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Ball # Signal Name J36 HD_51# HD_9# K34 HD_10# K36 HD_11# Ball # Table 7-2.
Ballout and Package Information Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Signal Name 166 Ball # Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Signal Name Ball # Table 7-2.
Ballout and Package Information Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Signal Name Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Ball # Signal Name Ball # Table 7-2.
Ballout and Package Information Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Signal Name 168 Ball # Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Signal Name Ball # Table 7-2.
Ballout and Package Information Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Signal Name Table 7-2. Intel® 82845G GMCH Ballout by Signal Name Ball # Signal Name Ball # Table 7-2.
Ballout and Package Information 7.2 Package Information The GMCH is in a 37.5 mm x 37.5 mm FC-BGA package with 1 mm ball pitch. Figure 7-3 and Figure 7-4 show the package dimensions. Figure 7-3. Intel® 82845G GMCH Package Dimensions (Top and Side Views) Top View Detail A 37.50 ±0.050 17.9250 18.75 Detail A 18.75 17.9250 37.50 ±0.05 16.9500 Detail B Detail C 16.9500 Side View 0.500 ±0.070 Die Substrate See Detail D 1.08 ±0.06 A 0.200 0.203 C A B ϕ 0.6500 ±0.05 ϕ 0.
Ballout and Package Information Figure 7-4. Intel® 82845G GMCH Package Dimensions (Bottom View) Bottom View Detail A 0.7500 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0.7500 37 AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G 1.0000 F E D C B A 1.0000 Detail B Detail B Pin A1 0.57 ±0.1 Detail A BGA Land; 760 balls ϕ 0.600 (760 places) 0.203 L 0.7 ±0.05 0.7 ±0.05 0.57 ±0.1 0.
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Testability 8 Testability In the GMCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it. 8.1 XOR Test Mode Initialization XOR test mode can be entered by driving GSBA[6] and GSBA[7] low, and TESTIN# low, and PWROK low, and RSTIN# low, then drive PWROK high, then RSTIN# high. XOR test mode via TESTIN# does not require a clock. 8.
Testability Table 8-2.
Testability Table 8-2.
Testability Table 8-3.
Testability Table 8-3.
Testability Table 8-4.
Testability Table 8-4.
Testability 8.3 XOR Chains Excluded Pins Table 8-5 lists the signals that are excluded from the XOR chains. Table 8-5.
Intel® 82845GL/82845GV GMCH Intel® 82845GL/82845GV GMCH 9 Chapter 1 through Chapter 8 of this datasheet described the 82845G component. The first eight chapters also apply to the 82845GL/82845GV with the differences noted in this chapter. This chapter describes the differences between the 82845G and 82845GL/82845GV components. Figure 9-1 is a system block diagram of an 845GL/845GV chipset-based system.
Intel® 82845GL/82845GV GMCH 9.2 No AGP Interface The 82845GL and 82845GV do not have an AGP interface. References to AGP in this document only apply to the 82845G component. For example, Chapter 2 describes how the 82845G DVO signals are multiplexed with the AGP signals. For the 82845GL/82845GV, the DVO signals are NOT multiplexed. In addition, AGP related registers are NOT in the 82845GL/82845GV components (see Section 9.4). 9.
Intel® 82845GL/82845GV GMCH 9.4 Intel® 82845G and Intel® 82845GL/82845GV Register Differences Chapter 3 describes the registers for the 82845G GMCH. This section describes the changes to Chapter 3 for the 82845GL/82845GV GMCH. The differences are in the Device 0 and Device 1 register sets. The Device 2 registers are the same for the 82845G and 82845GL/82845GV. 9.4.1 DRAM Controller/Host-Hub Interface Device Registers (Device 0) 9.4.1.
Intel® 82845GL/82845GV GMCH ATTBASE — Aperture Translation Table Register (Device 0) Address Offset Size: B8–BBh 32 bits AMTT — AGP MTT Control Register (Device 0) Address Offset Size: BC–BFh 8 bits LPTT — AGP Low Priority Transaction Timer Register (Device 0) Address Offset Size: 9.4.1.2 BDh 8 bits Device 0 Register Bit Differences The registers described in this section are in both the 82845G and 82845GL/82845GV.
Intel® 82845GL/82845GV GMCH GMCHCFG—GMCH Configuration Register (Device 0) Address Offset Default Value Access Size: C6–C7h 0C01h R/W, RO 16 bits Bits Description 12 Core/PSB Frequency Select (PSBFREQ)—RO. The default value of this bit is set by the strap assigned to pin PSBSEL and is latched at the rising edge of PWROK. (82845GL Only) 0 = PSB frequency is 400 MHz (PSBSEL sampled high on PWROK assertion) 1 = Indicates a processor running 533 MHz on the board.
Intel® 82845GL/82845GV GMCH CAPREG—Capability Identification Register (Device 0) Address Offset Default Value Access Size: 9.4.2 E4h–E8h 0x_x105_A009h RO 40 bits Bits Description 15:8 Next_Pointer. This field has the value A0h pointing to the next capabilities register, AGP Capability Identifier Register (ACAPID). Since AGP is disabled (IGDIS = 0), this becomes the last pointer in the device, and it is set to 00h signifying the end of the capabilities linked list.
Intel® 82845GL/82845GV GMCH Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Signal Name Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Ball# Signal Name Ball# Table 9-1.
Intel® 82845GL/82845GV GMCH Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Signal Name 188 Ball# Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Signal Name Table 9-1.
Intel® 82845GL/82845GV GMCH Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Signal Name Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Ball# Signal Name Ball# Table 9-1.
Intel® 82845GL/82845GV GMCH Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Signal Name 190 Ball# Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Signal Name Ball# Table 9-1.
Intel® 82845GL/82845GV GMCH Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Signal Name Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Ball# Signal Name Ball# Table 9-1.
Intel® 82845GL/82845GV GMCH Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Signal Name 192 Ball# Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Signal Name Ball# Table 9-1.
Intel® 82845GL/82845GV GMCH Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Signal Name Table 9-1. Intel® 82845GL/ 82845GV Ballout by Signal Name Ball# Signal Name Ball# Table 9-1.