Product specifications

Source Code
27
checksum = self.conn.read(1)
self.conn.close()
#self._verify_checksum(bytes, checksum)
reg0, reg1, reg2, reg3, reg4, reg5 = struct.unpack('>IIIIII', bytes)
low_spur = ((reg2 >> 30) & 1) & ((reg2 >> 29) & 1)
double = (reg2 >> 25) & 1
half = (reg2 >> 24) & 1
r = (reg2 >> 14) & 0x03ff
return double, half, r, low_spur
def set_options(self, synth, double = 0, half = 0, r = 1, low_spur = 0):
"""
Set options.
double and half both True is same as both False.
@param synth : synthesizer base address
@type synth : int
@param double : if 1, reference frequency is doubled; default 0
@type double : int
@param half : if 1, reference frequency is halved; default 0
@type half : int
@param r : reference frequency divisor; default 1
@type r : int
@param low_spur : if 1, minimizes PLL spurs;
if 0, minimizes phase noise; default 0
@type low_spur : int
@return: True if success (bool)
"""
self.conn.open()
bytes = struct.pack('>B', 0x80 | synth)
self.conn.write(bytes)
bytes = self.conn.read(24)
checksum = self.conn.read(1)
#self._verify_checksum(bytes, checksum)
reg0, reg1, reg2, reg3, reg4, reg5 = struct.unpack('>IIIIII', bytes)
reg2 &= 0x9c003fff
reg2 |= (((low_spur & 1) << 30) | ((low_spur & 1) << 29) |
((double & 1) << 25) | ((half & 1) << 24) |
((r & 0x03ff) << 14))
bytes = struct.pack('>BIIIIII', 0x00 | synth,
reg0, reg1, reg2, reg3, reg4, reg5)
checksum = self._generate_checksum(bytes)
self.conn.write(bytes + checksum)
bytes = self.conn.read(1)
self.conn.close()
ack = struct.unpack('>B', bytes)[0]
return ack == ACK
def get_ref_select(self):
"""Returns the currently selected reference clock.
Returns 1 if the external reference is selected, 0 otherwise.
"""
self.conn.open()
bytes = struct.pack('>B', 0x86)
self.conn.write(bytes)
bytes = self.conn.read(1)
checksum = self.conn.read(1)
self.conn.close()
#self._verify_checksum(bytes, checksum)
is_ext = struct.unpack('>B', bytes)[0]
return is_ext & 1