- Texas Instruments Floating Point Digital Signal Processor Specification Sheet

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   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
83
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
BUSREQ TIMING
switching characteristics over recommended operating conditions for the BUSREQ cycles
(see Figure 39)
NO. PARAMETER
GDPA-167
ZDPA−167
−200
−250
UNIT
MIN MAX
1 t
d(EKOH-BUSRV)
Delay time, ECLKOUT high to BUSREQ valid 1.5 7.2 ns
ECLKOUT
1
BUSREQ
1
Figure 39. BUSREQ Timing