- Texas Instruments Floating Point Digital Signal Processor Specification Sheet

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   
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
72
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Not Ready Hold = 2
BE
Address
Read Data
21
21
21
21
5
4
3
ARDY
77
66
5
ECLKOUT
CEx
EA[21:2]
ED[31:0]
AOE
/SDRAS/SSOE
†
ARE
/SDCAS/SSADS
†
BE[3:0]
AWE/SDWE/SSWE
†
†
AOE
/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 27. Asynchronous Memory Read Timing