user manual

Programming Considerations
http://www.motorola.com/computer/literature 2-11
2
Interrupt Handling
The Raven ASIC, which controls PHB (PCI Host Bridge) MPU/local bus
interface functions on the MVME2603/2604, performs interrupt handling
as well. Sources of interrupts may be any of the following:
❏ The Raven ASIC itself (timer interrupts or transfer error interrupts)
❏ The processor (processor self-interrupts)
❏ The Falcon chip set (memory error interrupts)
❏ The PCI bus (interrupts from PCI devices)
❏ The ISA bus (interrupts from ISA devices)
Figure 2-3 illustrates interrupt architecture on the MVME2603/2604. For
details on interrupt handling, refer to the MVME2600 Series Single Board
Computer Programmer’s Reference Guide, listed in Appendix D, Related
Documentation.