User`s manual

Glossary

GL-10

unified (instruction and data) cache. It provides a 64-bit

data bus and a separate 32-bit address bus. PowerPC 601 is

used by Motorola, Inc. under license from IBM.

PowerPC 603™ The second implementation of the PowerPC family of

microprocessors. This CPU incorporates a memory

management unit with a 64-entry buffer and an 8KB

(instruction and data) cache. It provides a selectable 32-bit

or 64-bit data bus and a separate 32-bit address bus.

PowerPC 603 is used by Motorola, Inc. under license from

IBM.

PowerPC 604™ The third implementation of the PowerPC family of

microprocessors currently under development. PowerPC

604 is used by Motorola, Inc. under license from IBM.

PowerPC Reference Platform (PRP)

A specification published by the IBM Power Personal

Systems Division which defines the devices, interfaces, and

data formats that make up a PRP-compliant system using a

PowerPC processor.

PowerStack™ RISC PC (System Board)

A PowerPC-based computer board platform developed by

the Motorola Computer Group. It supports MicrosoftÕs

Windows NT and IBMÕs AIX operating systems.

PRP See PowerPC Reference Platform (PRP).

PRP-compliant See PowerPC Reference Platform (PRP).

PRP Spec See PowerPC Reference Platform (PRP).

PROM Programmable Read-Only Memory

PS/2 Personal System/2 (IBM)

QFP Quad Flat Package

RAM Random-Access Memory. The temporary memory that a

computer uses to hold the instructions and data currently

being worked with. All data in RAM is lost when the

computer is turned off.

RAS Row Address Strobe. A clock signal used in dynamic RAMs

to control the input of the row addresses.