User Guide

1-4

Introduction

PCI Overview

Peripheral Component Interconnect (PCI) was developed by IntelÕs

Architecture Lab, along with leading computer vendors, to

overcome the bottlenecks associated with traditional 16-bit

expansion slots, operating at 8 MHz, or essentially 5 megabytes per

second. The result was a local bus system capable of transferring 32

bits of data at 33 MHz for a maximum data transfer rate of 132

megabytes per second. The PCI Local Bus takes peripherals off the

I/O bus and connects them together with the CPU and the memory

subsystem. This provides a wider, faster pathway for data, which is

especially important for servers, graphic-intensive software,

high-speed networks, and other high performance peripherals.

Features of the PCI Local Bus architecture include:

❏

Processor-independent bridge, between the CPU and

high-speed peripherals, that serves as a traffic controller

between busses.

❏

32-bit memory addressing for CPU, Direct Memory Access

(DMA) devices and bus masters.

❏

32-bit data transfers at 33 MHz for CPU, DMA and bus

master devices.

❏

132 Mbps maximum data transfer rate.

❏

Data is written and read from the peripherals in linear busts

at every clock cycle.

❏

Buffers located between the peripherals and the CPU that

allows multiple, high-speed peripherals to be attached to the

same PCI local bus.

❏

Automatic translation of bus cycles between PCI and the

traditional I/O slots for EISA, ISA, and MicroChannel busses.

❏

Automatic configuration of system and expansion boards.