User`s manual

SUPPORT INFORMATION
MPC505EVBUM/D 4-11
Table 4-8. P8 Expansion Connector Pin Assignments (continued)
Pin Mnemonic Signal
C-4 BI* BURST INHIBIT – Active-low input signal that indicates the slave does
not support burst mode.
C-5, C-6 IRQ3* IRQ2* INTERRUPT REQUEST (3, 2) – Prioritized active low input lines that
requests MCU synchronous interrupts. IRQ1* has the highest priority.
C-7, C-8 IRQ1*, IRQ0* INTERRUPT REQUEST (1, 0) – Prioritized active low input lines that
requests MCU synchronous interrupts. IRQ1* has the highest priority.
C-9 MODCK CLOCK MODE SELECT – Active-high input signal that selects the
source of the internal system clock.
C-10, C-11 NC Not Connected
C-12 GND GROUND
C-13 BURST* BURST – Active low indicates a burst cycle.
C-14 C-17 WP0* – WP3* WATCHPOINT (0 - 3) - Output signals for instruction bus (I-bus)
watchpoint.
C-18, C-19 WP4*, WP5* WATCHPOINT (4, 5) - Output signals for load/store bus (L-bus)
watchpoint.
C-20 NC Not Connected
C-21 AT0 ADDRESS TYPES bit 0 – One of two output bits that defines address
space as: user data, user instruction, supervisor data, or supervisor
instruction.
C-22 ECROUT ENGINEERING CLOCK REFERENCE OUT Clock reference for
peripheral chips.
C-23 C-26 BE0* BE3* BYTE ENABLE (03) Active-low output signals where one byte enable
controls one byte lane of the data bus.
C-27 NC Not Connected
C-28 CR* CANCEL RESERVATION Active-low input that instructs the bus master
to clear the external device's reservation.
C-29 PDWU POWER DOWN WAKEUP Output signal sends a power-down wakeup
to external power-on reset circuits.
C-30 NC Not Connected
C-31, C-32 GND GROUND