User`s manual

SUPPORT INFORMATION
4-10 MPC505EVBUM/D
Table 4-8. P8 Expansion Connector Pin Assignments (continued)
Pin Mnemonic Signal
A-21 NC Not Connected
A-22 ARETRY* ADDRESS PHASE RETRY – An active-low input signal that indicates
the master needs to retry its address phase.
A-23 BG* BUS GRANT – Active-low input signal that indicates that an external
device has assumed control of the bus.
A-24 BR* BUS REQUEST – Active-low input signal that indicates that an external
device requests bus mastership.
A-25 BB* BUS BUSY – Active-low, bi-directional signal asserted by the current
master that indicates that the bus is in use.
A-26 RESET* RESET – Active-low, input signal that resets the MPC505 MCU.
A-27 SRESET* SYSTEM RESET – Active-low, MPC505 MCU output signal that resets
the EVB.
A-28, A-29 VFLS1,
VFLS0
VISIBILITY FLUSH – History buffer flush status bits that indicate how
many instructions are flushed from the history buffer during the current
clock cycle. Also indicates the freeze state.
A-30 DSDI DEVELOPMENT SERIAL DATA IN – Serial data input signal for debug
mode.
A-31 DSCK DEVELOPMENT SERIAL CLOCK – Serial input clock for background
debug mode.
A-32 DSDO DEVELOPMENT SERIAL DATA OUT – Serial data output signal for
debug mode.
B-1, B-2 V3.3 +3.3 VDC POWER – Voltage generated by the on-board voltage
converter for use by the MPC505 MCU logic circuits.
B-3 B-29 GND GROUND
B-30 B-32 VCC +5 VDC POWER – Input voltage (+5 Vdc @ 2.0 A) used by the EVB
logic circuits.
C-1, C-2 V3.3 +3.3 VDC POWER – Voltage generated by the on-board voltage
converter for use by the MPC505 MCU logic circuits.
C-3 BDIP* BURST DATA IN PROGRESS – An active-low output signal that
indicates the data beat in front of the current one is needed by the
master.