User`s manual

SUPPORT INFORMATION
MPC505EVBUM/D 4-9
Table 4-7. Input Power Connector P7 Pin Assignments
Pin Mnemonic Signal
1 VCC +5 VDC POWER – Input voltage (+5 Vdc @ 2.0 A) used by the EVB
logic circuits. The "VCC" write on the board nere the coresponding pin.
2 GND GROUND The "GND" write on the board nere the coresponding pin
3 GND GROUND The "GND" write on the board nere the coresponding pin
Table 4-8. P8 Expansion Connector Pin Assignments
Pin Mnemonic Signal
A-1, A-2 V3.3 +3.3 VDC POWER – Voltage generated by the on-board voltage
converter for use by the MPC505 MCU logic circuits.
A-3 AACK* ADDRESS ACKNOWLEDGE – An active-low input signal that indicates
the slave has received the address from the bus master.
A-4 TS* TRANSFER START – An active-low output signal that indicates the
start of a bus cycle.
A-5 VDDSYN VDDSYN – Clock synthesizer power.
A-6 A-8 IRQ6* –
IRQ4*
INTERRUPT REQUEST (6 -4) – Prioritized active low input lines that
requests MCU synchronous interrupts. IRQ1* has the highest priority.
A-9 A-12 CT0 CT3 CYCLE TYPE SIGNALS – Four bits that indicate what type of bus cycle
the bus master is initiating.
A-13 GND GROUND
A-14 A-16 VF0 VF2 VISIBILITY FETCH – Instruction queue status bits that indicate the last
fetched instruction or the number of instructions flushed from the
instruction queue.
A-17 R_W* READ/WRITE – Active-high output signal that indicates the direction of
data transfer on the bus.
A-18 TA* TRANSFER ACKNOWLEDGE – An active-low input signal that
indicates the slave has received data during a write cycle or returned
data during a read cycle.
A-19 TEA* TRANSFER ERROR ACKNOWLEDGE – An active-low input signal that
indicates bus error condition.
A-20 AT1 ADDRESS TYPES bit 1 – One of two output bits that defines address
space as: user data, user instruction, supervisor data, or supervisor
instruction.