User`s manual

SUPPORT INFORMATION
MPC505EVBUM/D 4-7
Table 4-5. Debug Mode Connector P5 Pin Assignments
Pin Mnemonic Description
1 VFLS0 VISIBILITY FLUSH - If VFLS0 and VFLS1 are high the MPC505 is in
background debug mode.
2 SRESET* SYSTEM RESET – Active-low, MPC505 MCU output signal that is
asserted by the MCU during reset.
3 GND GROUND
4 DSCK DEVELOPMENT SERIAL CLOCK – Serial input clock for background
debug mode.
5 GND GROUND
6 VFLS1 VISIBILITY FLUSH - If VFLS0 and VFLS1 are high the MPC505 is in
background debug mode.
7 RESET* RESET – Active-low, input signal that resets the MPC505 MCU.
8 DSDI DEVELOPMENT SERIAL DATA IN – Serial data input signal for debug
mode.
9 VCC +5 VDC POWER – Input voltage (+5 Vdc @ 2.0 A) used by the EVB
logic circuits.
10 DSDO DEVELOPMENT SERIAL DATA OUT – Serial data output signal for
debug mode.