User`s manual

HARDWARE PREPARATION AND INSTALLATION
MPC505EVBUM/D 2-13
Table 2-7. Data Bus Reset Configuration Word (continued)
Data
Bus
Bit
Configuration
Function
Effected
Effect of
Mode Select = 1
During Reset
Effect of
Mode Select = 0
During Reset
EVB
Default
Mode
[9:10] IMEMBASE[0:1] IMEMBASE
00
01
10
11
Block Placement
Start Addr: 0x0000 0000
End Addr: 0x000F FFFF
Start Addr: 0xFFF0 0000
End Addr: 0xFFFF FFFF
10
[11:12] LMEMBASE[0:1] LMEMBASE
00
01
10
11
SRAM Block Placement
Start address: 0x0000 0000
End address: 0x000F FFFF
Start address: 0xFFF0 0000
End address: 0xFFFF FFFF
11
13 Reset configuration
source for DATA[14:21]
Latch configuration from
external pins
Latch configuration from
internal defaults.
1
14 CT[0:3], AT[0:1], TS CT[0:3], AT[0:1], TS PJ[1:7] 1
15 WR, BDIP WR, BDIP PK[0:1] 0
16 PLLL/DSDO, VF[0:2],
VFLS[0:1], WP[1:5]
DSDO, Pipe Tracking,
Watchpoints
PK[2:7], PL[2:7] 1
17 BURST, TEA, AACK,
TA, BE[0:3]
Handshake Pins PORTI[0:7] 1
18 CR, BI, BR, BB, BG,
ARETRY
Bus Arbitration Pins PM[2:7] 1
19 Release reset when PLL
locked
Release reset when PLL
locked and after 16 clocks
(when not in PLL 1:1
mode)
Hold reset 16 clocks after reset
negated.
1
20 Reserved 0
21 Reset Configuration
Source For DATA[22:31]
Latch Configuration from
external pins.
Latch Configuration from
internal defaults.
1
22 Reserved 0
23 IEN I-bus Memory modules
are enabled.
I-bus Memory modules are
disabled and emulated
externally.
0