MPC505EVB/D March 1997 MPC505EVB EVALUATION BOARD USER’S MANUAL © MOTOROLA Inc.
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
CONTENTS CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 GENERAL INFORMATION INTRODUCTION............................................................................................................. 1-1 FEATURES....................................................................................................................... 1-1 GENERAL DESCRIPTION ............................................................................................. 1-2 SPECIFICATIONS .................................................
CONTENTS CHAPTER 3 FUNCTIONAL DESCRIPTION 3.1 3.2 3.3 INTRODUCTION............................................................................................................. 3-1 EVB DESCRIPTION........................................................................................................ 3-1 MCU SUMMARY ............................................................................................................ 3-3 3.3.1 32-Bit Central Processor Unit............................................
CONTENTS TABLES 1-1. 1-2. 2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 2-7. 2-8. 2-9. 4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 4-7. 4-8. 4-9. 4-10. 4-11. 4-12. 4-13. 4-14. 4-15. EVB Specifications ........................................................................................................... 1-3 External Equipment Requirements ................................................................................... 1-4 Jumper Header Types........................................................................................
CONTENTS vi MPC505EVB/D *PRELIMINARY
GENERAL INFORMATION CHAPTER 1 GENERAL INFORMATION 1.1 INTRODUCTION This manual provides general information, hardware preparation, installation instructions, and support information for the MPC505EVB Evaluation Board (EVB). The EVB lets you evaluate PowerPC MPC505 RISC Microcontrollers. 1.
GENERAL INFORMATION 1.3 GENERAL DESCRIPTION The EVB is a low-cost tool for evaluating and debugging MPC505 MCU-based systems. The MPC505 MCU device is an advanced single-chip MCU with on-chip memory and peripheral functions. For more information refer to the PowerPC MPC505 RISC Microcontroller Technical Summary (MPC505TS/D). The EVB includes a monitor/debugging program (MPCbug) that demonstrates the capabilities of the MPC505.
GENERAL INFORMATION to 2 megabytes by replacing the devices at locations U24, U25, U27, and U28 with larger devices. The flash memory devices require +5 volts. There are a total of eight 52-pin PLCC sockets on the EVB (U19, U20, U21, U22, U29, U30, U31, and U32) for synchronous static RAM (SSRAM) devices. These sockets are paired as upper and lower words and organized for long-word (32 bits wide) data transfers. Each pair is referred to as BANKx.
GENERAL INFORMATION 1.5 EQUIPMENT REQUIRED Table 1-2 lists the external equipment requirements for EVB operation. Table 1-2.
HARDWARE PREPARATION AND INSTALLATION CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION 2.1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the EVB. Chapter 6 is a description of the EVB Diagnostic Monitor (MPCdiag). 2.2 HARDWARE PREPARATION This paragraph describes the preparation of EVB components prior to use. These preparations ensure that the EVB components are properly configured.
HARDWARE PREPARATION AND INSTALLATION Figure 2-1.
HARDWARE PREPARATION AND INSTALLATION Table 2-1. Jumper Header Types Jumper Header Type Symbol Description two-pin with solder strap Two-pin plate through holes (without jumper header block) and designated as JX (X = the jumper header number). Bus wire soldered between the two pins of the plate through holes to create a short. two-pin Two-pin jumper header and designated as JX (X = the jumper header number). Use a fabricated jumper to create a short between the two pins of the jumper header.
HARDWARE PREPARATION AND INSTALLATION Table 2-2. MPFB Jumper Header Descriptions (continued) Jumper Header Type J4 321 Keep alive power 1 select header System clock selection header J7 System clock selection header 2-4 Jumper installed on pins 1 and 2 (factory default); MCU-internal oscillator, time base, and decrementer operates as long as power is applied to the EVB (+3.3 Vdc present on the VKAPWR2 pin of the MCU). +3.
HARDWARE PREPARATION AND INSTALLATION 2.2.1 Crystal Clock Select Header (J1) Jumper header J1 connects the crystal clock to the MCU XTAL pin clock source. The drawing below shows the factory configuration: bus wire soldered on pins 1 and 2. This configuration selects the crystal clock source; crystal in socket at located Y1. When you want to use the clock oscillator as the EVB clock, remove the bus wire on J1 and move the bus wire on J2 from pins 2 and 3 to pins 1 and 2 (see paragraph 2.2.2).
HARDWARE PREPARATION AND INSTALLATION 2.2.2 Clock Source Select Header (J2) Use jumper header J2 to select either a crystal or clock oscillator as the MCU clock source. The drawing below shows the factory configuration: bus wire soldered on pins 2 and 3. This configuration selects the crystal clock source; crystal in socket at located Y1. When you want to use the clock oscillator as the EVB clock, move the bus wire on J2 from pins 2 and 3 to pins 1 and 2 and remove the bus wire on J1 (see paragraph 2.2.
HARDWARE PREPARATION AND INSTALLATION 2.2.4 Keep Alive Power 2 Select Header (J4) Jumper header J3 provides power to the MCU-internal oscillator, time base, and decementer modules via the MCU VKAPWR1 pin. You may use either the on-board +3.3 Vdc (jumper on J4 pins 1 and 2) or connect an external +3.3 Vdc power supply to J4 pins 2 and 3. An external +3.3 Vdc power supply on J4 pins 2 and 3 will maintain MCU-internal RAM data after EVB power is turned OFF.
HARDWARE PREPARATION AND INSTALLATION 2.2.6 System Clock Selection Headers (J6 and J7) Jumper headers J6 and J7 let you define the system clock source. The factory configuration (shown below) is for normal operation; a fabricated jumper on J6 and J7 pins 1 and 2. Refer to Table 2-4 for configuring the system clock source. Table 2-4.
HARDWARE PREPARATION AND INSTALLATION 2.2.7 EVB LED Descriptions There are three LEDs on the EVB. Their functions are: 2.2.8 • LD1 – 3.3 Vdc power: ON = 3.3 Vdc power is applied to the EVB. • LD2 – Debug Mode: ON = MPC505 is in debug mode • LD3 – +5 Vdc power: ON = power is applied to the EVB. Optional Memory Configuration There are eight 52-pin PLCC sockets on the EVB (U19, U20, U21, U22, U29, U30, U31, and U32) for synchronous static RAM (SSRAM) devices.
HARDWARE PREPARATION AND INSTALLATION 2.2.9 EVB Reset Switches There are two reset switches on the EVB: • Switch SW1 lets you reset the MPC505 MCU • Switch SW2 lets you reset the EVB. 2.2.10 EVB DIP Switches There are six DIP switches on the EVB (DS1 – DS6): 2-10 • DS1 – Attaches the MCU chip selects to the EVB on-board memory and peripheral devices. You may disable on-board chip selects and connect them via the expansion connectors (P6 and P8) to external memory or peripheral devices.
HARDWARE PREPARATION AND INSTALLATION 2.2.10.1 Chip Select Dip Switch (DS1) The MPC505 MCU uses several chip selects on-board to control EVB functionality (memory and peripheral devices). You can redefine these chip selects to control external devices via the expansion connectors. To avoid conflicts between on-board and external devices, disable the appropriate chip select by setting the appropriate DS1 switch (see Table 2-6). Table 2-6.
HARDWARE PREPARATION AND INSTALLATION 2.3.10.2 Reset Data Dip Switches (DS2 – DS5) Dip switches DS2 – DS5 are connected through 4 buffers on the MPC505 MCU data bus (D31 – D0). At RESET the MCU reads the data bus and changes its configuration according to these switches ("ON" = 0 LOGIC). There are two reset configuration modes: data bus configuration mode (pertinent to the EVB) or internal default mode.
HARDWARE PREPARATION AND INSTALLATION Table 2-7.
HARDWARE PREPARATION AND INSTALLATION Table 2-7. Data Bus Reset Configuration Word (continued) Data Bus Bit Configuration Function Effected 24 LEN 25 PRUMODE 26 ADDR[12:15] Effect of Mode Select = 1 During Reset Effect of Mode Select = 0 During Reset EVB Default Mode L-bus Memory modules are enabled. L-bus Memory modules are disabled and emulated externally. 1 Forces accesses to Ports A, B, I, J, K, and L to go external.
HARDWARE PREPARATION AND INSTALLATION 2.2.10.3 DTE/DCE Settings DS6 switch 1 lets you define which connector to use with your host computer. While DS6 switches 2 - 4 lets you define I/O connectors P2, P3, and P4 as DTE or DCE. Table 2-8 shows DS6 switch settings. Table 2-8.
HARDWARE PREPARATION AND INSTALLATION 2.3 INSTALLATION INSTRUCTIONS The EVB is designed for table top operation. A user supplied power supply and host computer (with an RS-232C port) are required for EVB operation. 2.3.1 Host Computer – EVB Interconnection Interconnection of a host computer to the EVB is accomplished via a user supplied 25-pin flat cable assembly. One end of the cable assembly is connected to the EVB connector P4 (shown below).
HARDWARE PREPARATION AND INSTALLATION 2.3.2 Background Mode Connector (P5) Use connector P5 (pinouts shown below) to communicate with the EVB via the background debug mode (BDM). You may use the serial development interface (SDI) as your BDM interface. Connect one end of the SDI to your host computer and the other to connector P5. For more information about the SDI refer to the M68SDIUM Users Manual, M68SDIUM/D.
HARDWARE PREPARATION AND INSTALLATION 2.3.3 Power Supply – EVB Interconnection The EVB requires +5 Vdc @ 2 amp power supply for operation. Connector P7 pin 1 is +5 Vdc; pins 2 and 3 are ground (shown in Figure 2-2). Use 16-22 AWG wire in the connector (supplied with the board). EVB power supply interconnection for connector P7 is shown below. Figure 2-2.
HARDWARE PREPARATION AND INSTALLATION 2.3.4 RS-232C – EVB Interconnection Interconnection of an RS-232C compatible device to the EVB is accomplished via a user supplied 9-pin cable assembly. One end of the cable assembly is connected to either EVB port P2 or P3 (shown below). The other end of the cable assembly is connected to the user supplied RS232C compatible device. For connector pin assignments and signal descriptions of the EVB RS232C ports P2 and P3, refer to Appendix B.
HARDWARE PREPARATION AND INSTALLATION 2.3.5 EVB Expansion Connectors There are two expansion connectors (P6 and P8) on the EVB. The pin assignments for the expansion connectors are in Figures 2-3 and 2-4. Signal descriptions are in Appendix B.
HARDWARE PREPARATION AND INSTALLATION C B A +3.3 Vdc 1 • +3.3 Vdc 1 • +3.3 Vdc 1 • +3.3 Vdc 2 • +3.3 Vdc 2 • +3.
HARDWARE PREPARATION AND INSTALLATION 2.3.6 Logic Analyzer Connectors Use connectors POD1 through POD7 to connect a logic analyzer to the circuit being evaluated. Below are the pin assignments for the logic analyzer connectors.
HARDWARE PREPARATION AND INSTALLATION POD5 POD6 NC 1 • • 2 NC NC 1 • • 2 NC NC 3 • • 4 DSCK NC 3 • • 4 CLKOUT DSDI 5 • • 6 DSDO RESET~ 5 • • 6 SRESET~ VF0 7 • • 8 VF1 CT0 7 • • 8 CT1 VF2 9 • • 10 VFLS0 CT2 9 • • 10 CT3 VFLS1 11 • • 12 WP0~ CR~ 11 • • 12 BR~ WP1~ 13 • • 14 WP2~ BB~ 13 • • 14 BG~ WP3~ 15 • • 16 WP4~ IRQ0~ 15 • • 16 IRQ1~ WP5~ 17 • • 18 NC ECROUT 17 • • 18 MODCLK NC 19 • • 20 GND PDWU 19 • • 20
HARDWARE PREPARATION AND INSTALLATION 2-24 MPC505EVBUM/D
FUNCTIONAL DESCRIPTION CHAPTER 3 FUNCTIONAL DESCRIPTION 3.1 INTRODUCTION This chapter is a functional description of the EVB and its components. 3.2 EVB DESCRIPTION The EVB may be configured in either of two ways; the BCC mounted on the PFB or the BCC mounted on the target system. Figure 3-1 is the EVB block diagram. When the BCC is mounted on the PFB, you may evaluate the MCU and debug user developed code.
FUNCTIONAL DESCRIPTION Figure 3-1.
FUNCTIONAL DESCRIPTION 3.3 MCU SUMMARY The resident MC68332 Microcontroller Unit (MCU) of the BCC provides resources for designing, debugging, and evaluating MC68332 MCU based target systems and simplifies user evaluation of prototype hardware/software products. The MCU device is a 32-bit integrated microcontroller, combining high-performance data manipulation capabilities with powerful peripheral subsystems.
FUNCTIONAL DESCRIPTION 3.3.2 Time Processor Unit The Time Processor Unit (TPU) optimizes performance of time-related activities. The TPU has a dedicated execution unit, tri-level prioritized scheduler, data storage RAM, dual time bases, and microcode ROM which drastically reduces the need for CPU intervention. The TPU controls sixteen independent, orthogonal channels; each channel has an associated I/O pin and can perform any time function.
FUNCTIONAL DESCRIPTION 3.3.5 External Bus Interface The external bus consists of 24 address lines and a 16-bit data bus. The data bus allows dynamic sizing between 8- and 16-bit data accesses. A read-modify-write cycle (RMC) signal prevents bus cycle interruption. External bus arbitration is accomplished by a three-line handshaking interface. 3.3.6 Chip Selects Twelve independently programmable chip selects provide fast, two-cycle external memory, or peripheral access.
FUNCTIONAL DESCRIPTION XXX7FF INTERNAL RAM (2) (1 ) XXX000 FFFFFF MCU INTERNAL MODULES FFF000 OPTIONAL FPCP (3) PFB: U5 FFE800 800000 ALTERNATE MCU INTERNAL MODULES LOCATION (4) 7FF000 OPTIONAL RAM/EPROM PFB: U2 & U4 CPU32BUG EPROM BCC: U1 & U2 110000 /120000 (5) 100000 0E0000 OPTIONAL RAM PFB: U1 & U3 TARGET RAM BCC: U3 & U4 SYSTEM RAM BCC: U3 & U4 1. 2. 3. 4. 5.
FUNCTIONAL DESCRIPTION 3.5 I/O CONNECTORS There are two 64-pin expansion connectors on the BCC (P1 and P2). Through these connectors the BCC communicates with the PFB or target system. Background mode operation is available through P3 and serial communication through P4. Chapter 5 contains a description of the interface connectors pin assignments. 3.5.1 64-Pin Expansion Connectors The expansion connectors interconnect the BCC to the PFB or target system.
FUNCTIONAL DESCRIPTION The coprocessor interface is a transparent, logical extension of the MC68332 MCU device registers and instructions. To the external environment the CPU and coprocessor execution model appear to be on the same chip. A coprocessor interface is an execution model based on sequential instruction execution by the CPU and coprocessor. For optimum performance, the coprocessor interface lets floating point instructions execute concurrently with CPU integer instructions.
SUPPORT INFORMATION CHAPTER 4 SUPPORT INFORMATION 4.1 INTRODUCTION The tables in this chapter describe EVB connector signals. 4.2 CONNECTOR SIGNAL DESCRIPTIONS The following are all the connectors on the board include pin number mnemonic and signal description. Connector P7 connects external power to the EVB. the host computer connects to the EVB via P4. POD1 through POD7 let you connect a logic analyzer to the EVB. P2 and P3 are EVB I/O ports for evaluating RS-232C devices.
SUPPORT INFORMATION Table 4-1. SCSI Connector (not populated) 4-2 Pin Mnemonic Signal 1 GND GROUND 2 SDB0 SCSI DATA BUS (bit 0) – Bit 0 of the SCSI bi-directional data bus lines. 3 GND GROUND 4 SDB1 SCSI DATA BUS (bit 1) – Bit 1 of the SCSI bi-directional data bus lines. 5 GND GROUND 6 SDB2 SCSI DATA BUS (bit 2) – Bit 2 of the SCSI bi-directional data bus lines. 7 GND GROUND 8 SDB3 SCSI DATA BUS (bit 3) – Bit 3 of the SCSI bi-directional data bus lines.
SUPPORT INFORMATION Table 4-1. SCSI Connector (not populated) (continued) Pin Mnemonic 27 – 31 GND GROUND 32 ATNI* ATTENTION – Active-low output signal that indicates to the target that the MPC505 has a message to send. 33 – 35 GND GROUND 36 BSY BUSY – Active low I/O signal that indicates the SCSI is busy. 37 GND GROUND 38 ACK ACKNOWLEDGE – Active-low handshake signal that indicates to the target that the MPC505 has transfered a byte.
SUPPORT INFORMATION Table 4-2. RS-232C I/O Connector P2 Pin Assignments Pin Mnemonic Signal 1 ADCD* DATA CARRIER DETECT – An output signal used to indicate an acceptable received line (carrier) signal has been detected. 2 ARXD RECEIVE DATA – RS-232C serial input signal. 3 ATXD TRANSMIT – RS-232C serial output signal. 4 ADTR* DATA TERMINAL READY – An output line that indicates an on-line/inservice/active status.
SUPPORT INFORMATION Table 4-3. RS-232C I/O Connector P3 Pin Assignments Pin Mnemonic 1 BDCD* DATA CARRIER DETECT – An output signal used to indicate an acceptable received line (carrier) signal has been detected. 2 BRXD RECEIVE DATA – RS-232C serial input signal. 3 BTXD TRANSMIT – RS-232C serial output signal. 4 BDTR* DATA TERMINAL READY – An output line that indicates an on-line/inservice/active status.
SUPPORT INFORMATION Table 4-4. Host Computer Connector P4 Pin Assignments 4-6 Pin Mnemonic Signal 1 NC 2 CTXD TRANSMIT – RS-232C serial output signal. 3 CRXD RECEIVE DATA – RS-232C serial input signal. 4 CRTS REQUEST TO SEND – An input signal used to request permission to transfer data. 5 CCTS* CLEAR TO SEND – An output signal that indicates a ready-to-transfer data status. 6 ADSR* DATA SET READY – An output signal (held high) that indicates an online/in-service/active status.
SUPPORT INFORMATION Table 4-5. Debug Mode Connector P5 Pin Assignments Pin Mnemonic 1 VFLS0 2 SRESET* 3 GND GROUND 4 DSCK DEVELOPMENT SERIAL CLOCK – Serial input clock for background debug mode. 5 GND GROUND 6 VFLS1 7 RESET* 8 DSDI DEVELOPMENT SERIAL DATA IN – Serial data input signal for debug mode. 9 VCC +5 VDC POWER – Input voltage (+5 Vdc @ 2.0 A) used by the EVB logic circuits. 10 DSDO DEVELOPMENT SERIAL DATA OUT – Serial data output signal for debug mode.
SUPPORT INFORMATION Table 4-6. P6 Expansion Connector Pin Assignments Pin Mnemonic A-1 FOE* FLASH OUTPUT ENABLE - Active low output signal that lets you read the EVB on-board flash memory. A-2 CS5* CHIP SELECT 5 Output signal that selects peripheral/memory devices at programmed addresses. A-3 A-13 A10 A20 A-14 GND A-15 A-30 D0 D15 A-31 GND A-32 NC B-1 B-3 VCC +5 VDC POWER –Input voltage (+5 Vdc @ 2.0 A) used by the EVB logic circuits.
SUPPORT INFORMATION Table 4-7. Input Power Connector P7 Pin Assignments Pin Mnemonic Signal 1 VCC +5 VDC POWER – Input voltage (+5 Vdc @ 2.0 A) used by the EVB logic circuits. The "VCC" write on the board nere the coresponding pin. 2 GND GROUND The "GND" write on the board nere the coresponding pin 3 GND GROUND The "GND" write on the board nere the coresponding pin Table 4-8. P8 Expansion Connector Pin Assignments Pin Mnemonic A-1, A-2 V3.
SUPPORT INFORMATION Table 4-8. P8 Expansion Connector Pin Assignments (continued) Pin Mnemonic A-21 NC A-22 ARETRY* ADDRESS PHASE RETRY – An active-low input signal that indicates the master needs to retry its address phase. A-23 BG* BUS GRANT – Active-low input signal that indicates that an external device has assumed control of the bus. A-24 BR* BUS REQUEST – Active-low input signal that indicates that an external device requests bus mastership.
SUPPORT INFORMATION Table 4-8. P8 Expansion Connector Pin Assignments (continued) Pin Mnemonic C-4 BI* BURST INHIBIT – Active-low input signal that indicates the slave does not support burst mode. C-5, C-6 IRQ3* IRQ2* INTERRUPT REQUEST (3, 2) – Prioritized active low input lines that requests MCU synchronous interrupts. IRQ1* has the highest priority. C-7, C-8 IRQ1*, IRQ0* INTERRUPT REQUEST (1, 0) – Prioritized active low input lines that requests MCU synchronous interrupts.
SUPPORT INFORMATION Table 4-9. Logic Analyzer Connector POD1 Pin Assignments Pin Mnemonic Signal 1, 2 NC Not Connected 3 TS* TRANSFER START – An active-low output signal that indicates the start of a bus cycle. 4 FOE* FLASH OUTPUT ENABLE - Active low output signal that lets you read the EVB on-board flash memory. 5–9 CS1* – CS5* CHIP SELECT (1 – 5) – Output signals that select peripheral/memory devices at programmed addresses.
SUPPORT INFORMATION Table 4-12. Logic Analyzer Connector POD4 Pin Assignments Pin Mnemonic 1–3 NC 4 – 19 D0 – D15 20 GND Signal Not Connected DATA BUS (bits 0 15) – Bi-directional data pins. GROUND Table 4-13. Logic Analyzer Connector POD5 Pin Assignments Pin Mnemonic Signal 1–3 NC 4 DSCK DEVELOPMENT SERIAL CLOCK – Serial input clock for background debug mode. 5 DSDI DEVELOPMENT SERIAL DATA IN – Serial data input signal for debug mode.
SUPPORT INFORMATION Table 4-14. Logic Analyzer Connector POD6 Pin Assignments Pin Mnemonic 1–3 NC 4 CLKOUT SYSTEM CLOCK OUT – Output signal that is the MPC505 MCU internal system clock. 5 RESET* RESET – Active-low, input signal that resets the MPC505 MCU. 6 SRESET* SYSTEM RESET – Active-low, MPC505 MCU output signal that resets the EVB. 7 – 10 CT0 – CT3 CYCLE TYPE SIGNALS – Four bits that indicate what type of bus cycle the bus master is initiating.
SUPPORT INFORMATION Table 4-15. Logic Analyzer Connector POD7 Pin Assignments Pin Mnemonic 1, 2 NC 3 CLKOUT 4 BURST 5 TEA* TRANSFER ERROR ACKNOWLEDGE – An active-low input signal that indicates bus error condition. 6 AACK* ADDRESS ACKNOWLEDGE – An active-low input signal that indicates the slave has received the address from the bus master.
SUPPORT INFORMATION 4-16 MPC505EVBUM/D
