Specifications

SUPPORT INFORMATION
4-12 MPC505EVBUM/D
Table 4-9. Logic Analyzer Connector POD1 Pin Assignments
Pin Mnemonic Signal
1, 2 NC Not Connected
3 TS* TRANSFER START – An active-low output signal that indicates the
start of a bus cycle.
4 FOE* FLASH OUTPUT ENABLE - Active low output signal that lets you read
the EVB on-board flash memory.
5 – 9 CS1* – CS5* CHIP SELECT (1 – 5) – Output signals that select peripheral/memory
devices at programmed addresses.
10 – 13 BSWE0* –
BSWE3*
Address signal A6 - A9 - one signal of the three-state output address
bus.
14 – 19 A10 – A15 ADDRESS BUS (bits 10 15) – 6-pins of the three-state output address
bus.
20 GND GROUND
Table 4-10. Logic Analyzer Connector POD2 Pin Assignments
Pin Mnemonic Signal
1 – 3 NC Not Connected
4 – 17 A16 – A29 ADDRESS BUS (bits 16 29) – 14-pins of the three-state output address
bus.
18 – 20 GND GROUND
Table 4-11. Logic Analyzer Connector POD3 Pin Assignments
Pin Mnemonic Signal
1 – 3 NC Not Connected
4 – 19 D16 – D31 DATA BUS (bits 16 31) – Bi-directional data pins.
20 GND GROUND
SUPPORT INFORMATION
MPC505EVBUM/D 4-13
Table 4-12. Logic Analyzer Connector POD4 Pin Assignments
Pin Mnemonic Signal
1 – 3 NC Not Connected
4 – 19 D0 – D15 DATA BUS (bits 0 15) – Bi-directional data pins.
20 GND GROUND
Table 4-13. Logic Analyzer Connector POD5 Pin Assignments
Pin Mnemonic Signal
1 – 3 NC Not Connected
4 DSCK DEVELOPMENT SERIAL CLOCK – Serial input clock for background
debug mode.
5 DSDI DEVELOPMENT SERIAL DATA IN – Serial data input signal for debug
mode.
6 DSDO DEVELOPMENT SERIAL DATA OUT – Serial data output signal for
debug mode.
7 – 9 VF0 – VF2 VISIBILITY FETCH – Instruction queue status bits that indicate the last
fetched instruction or the number of instructions flushed from the
instruction queue.
10, 11 VFLS0,
VFLS1
VISIBILITY FLUSH – History buffer flush status bits that indicate how
many instructions are flushed from the history buffer during the current
clock cycle. Also indicates the freeze state.
12 – 15 WP0* – WP3*WATCHPOINT (0 - 3) Output signals for instruction bus (I-bus)
watchpoint.
16, 17 WP4*, WP5* WATCHPOINT (4, 5) Output signals for load/store bus (L-bus)
watchpoint.
18, 19 NC Not Connected
20 GND GROUND
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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