Specifications

SUPPORT INFORMATION
4-8 MPC505EVBUM/D
Table 4-6. P6 Expansion Connector Pin Assignments
Pin Mnemonic Signal
A-1 FOE* FLASH OUTPUT ENABLE - Active low output signal that lets you read
the EVB on-board flash memory.
A-2 CS5* CHIP SELECT 5 Output signal that selects peripheral/memory devices
at programmed addresses.
A-3 A-13 A10 A20 ADDRESS BUS (bits 10 – 20) – 11-pins of the three-state output
address bus.
A-14 GND GROUND
A-15 A-30 D0 D15 DATA BUS (bits 0 15) – Bi-directional data pins.
A-31 GND GROUND
A-32 NC Not Connected
B-1 B-3 VCC +5 VDC POWER –Input voltage (+5 Vdc @ 2.0 A) used by the EVB
logic circuits.
B-4 BSWE2* Address signal A8 - one signal of the three-state output address bus.
B-5 BSWE0* Address signal A6 - one signal of the three-state output address bus.
B-6 B-9 CS4* CS1* CHIP SELECT (4 – 1) – Output signals that select peripheral/memory
devices at programmed addresses.
B-10 B-29 GND GROUND
B-30 CLKOUT SYSTEM CLOCK OUT – Output signal that is the MPC505 MCU
internal system clock.
B-31, B-32 GND GROUND
C-1 BSWE3* Address signal A9 - one signal of the three-state output address bus.
C-2 BSWE1* Address signal A7 - one signal of the three-state output address bus.
C-3 CSBT* BOOT CHIP SELECT – Active-low output signal that selects peripheral
or memory devices at programmed addresses.
C-4 C-12 A21 A29 ADDRESS BUS (bits 21 29) – 9-pins of the three-state output address
bus.
C-13 GND GROUND
C-14 C-29 D16 D31 DATA BUS (bits 16 31) – Bi-directional data pins.
C-30 GND GROUND
C-31, C-32 NC Not Connected
SUPPORT INFORMATION
MPC505EVBUM/D 4-9
Table 4-7. Input Power Connector P7 Pin Assignments
Pin Mnemonic Signal
1 VCC +5 VDC POWER – Input voltage (+5 Vdc @ 2.0 A) used by the EVB
logic circuits. The "VCC" write on the board nere the coresponding pin.
2 GND GROUND The "GND" write on the board nere the coresponding pin
3 GND GROUND The "GND" write on the board nere the coresponding pin
Table 4-8. P8 Expansion Connector Pin Assignments
Pin Mnemonic Signal
A-1, A-2 V3.3 +3.3 VDC POWER – Voltage generated by the on-board voltage
converter for use by the MPC505 MCU logic circuits.
A-3 AACK* ADDRESS ACKNOWLEDGE – An active-low input signal that indicates
the slave has received the address from the bus master.
A-4 TS* TRANSFER START – An active-low output signal that indicates the
start of a bus cycle.
A-5 VDDSYN VDDSYN – Clock synthesizer power.
A-6 A-8 IRQ6* –
IRQ4*
INTERRUPT REQUEST (6 -4) – Prioritized active low input lines that
requests MCU synchronous interrupts. IRQ1* has the highest priority.
A-9 A-12 CT0 CT3 CYCLE TYPE SIGNALS – Four bits that indicate what type of bus cycle
the bus master is initiating.
A-13 GND GROUND
A-14 A-16 VF0 VF2 VISIBILITY FETCH – Instruction queue status bits that indicate the last
fetched instruction or the number of instructions flushed from the
instruction queue.
A-17 R_W* READ/WRITE – Active-high output signal that indicates the direction of
data transfer on the bus.
A-18 TA* TRANSFER ACKNOWLEDGE – An active-low input signal that
indicates the slave has received data during a write cycle or returned
data during a read cycle.
A-19 TEA* TRANSFER ERROR ACKNOWLEDGE – An active-low input signal that
indicates bus error condition.
A-20 AT1 ADDRESS TYPES bit 1 – One of two output bits that defines address
space as: user data, user instruction, supervisor data, or supervisor
instruction.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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