Specifications

FUNCTIONAL DESCRIPTION
3-4 MPC505EVBUM/D
3.3.2 Time Processor Unit
The Time Processor Unit (TPU) optimizes performance of time-related activities. The TPU has a
dedicated execution unit, tri-level prioritized scheduler, data storage RAM, dual time bases, and
microcode ROM which drastically reduces the need for CPU intervention. The TPU controls
sixteen independent, orthogonal channels; each channel has an associated I/O pin and can
perform any time function. Each channel also contains a dedicated event register, for both match
and input capture functions.
Each channel can be synchronized to either of two 16-bit, free-running counters with a pre-scaler.
One counter, based on the system clock, provides resolution of TPU system clock divided by 4.
The second counter, based on an external reference, also provides resolution of TPU system
clock divided by 8. Channels may also be linked together, allowing the user to reference
operations on one channel to the occurrence of a specified action on another channel, providing
inter-task control.
3.3.3 Queued Serial Module
The QSM contains two serial ports. The queued serial peripheral interface (QSPI) port provides
easy peripheral expansion or inter-processor communications via a full-duplex, synchronous,
three-line bus: data-in, data-out, and a serial clock. Four programmable peripheral select pins
provide address-ability for as many as 16 peripheral devices. A QSPI enhancement is an added
queue in a small RAM. This lets the QSPI handle as many as 16 serial transfers of 8- to 16-bits
each, or to transmit a stream of data as long as 256 bits without CPU intervention. A special
wrap-around mode lets the user continuously sample a serial peripheral, automatically updating
the QSPI RAM for efficient interfacing to serial peripheral devices (such as analog-to-digital
converters).
The serial communications interface (SCI) port provides a standard non-return to zero (NRZ)
mark/space format. Advanced error detection circuitry catches noise glitches to 1/16 of a bit time
in duration. Word length is software selectable between 8- or 9-bits, and the SCI modulus-type,
baud rate generator provides baud rates from 64 to 524k baud, based on a 16.77 MHz system
clock. The SCI features full- or half-duplex operation, with separate transmitter and receiver
enable bits and double buffering of data. Optional parity generation and detection provide either
even or odd parity check capability. Wake-up functions let the CPU run uninterrupted until either
a true idle line is detected or a new address byte is received.
3.3.4 Random Access Memory
2k bytes of static RAM are contained within the MC68332 MCU device. The RAM is used for
storage of variable and temporary data. RAM data size may be 8-bits (byte), 16-bits (word), or
32-bits (longword). The RAM can be mapped to any 2k byte boundary in the address map.
FUNCTIONAL DESCRIPTION
MPC505EVBUM/D 3-5
3.3.5 External Bus Interface
The external bus consists of 24 address lines and a 16-bit data bus. The data bus allows dynamic
sizing between 8- and 16-bit data accesses. A read-modify-write cycle (RMC) signal prevents
bus cycle interruption. External bus arbitration is accomplished by a three-line handshaking
interface.
3.3.6 Chip Selects
Twelve independently programmable chip selects provide fast, two-cycle external memory, or
peripheral access. Block size is programmable from 2 kilobytes through 1 megabyte. Accesses
can be selected for either 8- or 16-bit transfers. As many as 13 wait states can be programmed for
insertion during the access. All bus interface signals are automatically handled by the chip select
logic.
3.3.7 System Clock
An on-chip phase locked loop circuit generates the system clock signal to run the device up to
16.78 MHz from a 32.768 kHz watch crystal. The system speed can be changed dynamically,
providing either high performance or low power consumption under software control. The
system clock is a fully-static CMOS design, so it is possible to completely stop the system clock
via a low power stop instruction, while still retaining the contents of the registers and on-board
RAM.
3.3.8 Test Module
The test module consolidates the microcontroller test logic into a single block to facilitate
production testing, user self-test, and system diagnostics. Scan paths throughout the MC68332
provide signature analysis checks on internal logic. User self-test is initiated by asserting the test
pin to enter test mode. This test provides a pass/fail response to various externally supplied test
vectors.
3.4 USER MEMORY
On board the BCC is 32k x 16 bits of RAM and 64k x 16 bits of EPROM. The RAM is the
debug monitor storage area and user accessible memory space; the M68MPCBUG Debug
Monitor is stored in the BCC EPROMs. For debug monitor functionality see the M68MPCBUG
Debug Monitor User’s Manual, M68MPCBUG /AD1. Figure 3-3 is the EVB memory map.
The PFB has sockets for 32k x 16 or 64k x 16 bit RAM or 64k x 16 bit EPROM. The RAM
and/or EPROM, supplied by the user, is user-accessible memory space.
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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