Specifications
HARDWARE PREPARATION AND INSTALLATION
2-12 MPC505EVBUM/D
2.3.10.2 Reset Data Dip Switches (DS2 – DS5)
Dip switches DS2 – DS5 are connected through 4 buffers on the MPC505 MCU data bus (D31 –
D0). At RESET the MCU reads the data bus and changes its configuration according to these
switches ("ON" = 0 LOGIC).
There are two reset configuration modes: data bus configuration mode (pertinent to the EVB) or
internal default mode. In either mode the configuration is set by the MCU driving a configuration
word onto the internal data bus. Table 2-7 describes the configuration options. The EVB Default
Mode column shows the default reset configuration word. The default reset data bus
configuration word is X9E5EF4A3. For information on the internal reset configuration mode
refer to the PowerPC MPC505 RISC Microcontroller Technical Summary, MPC505TS/D.
Table 2-7. Data Bus Reset Configuration Word
Data
Bus
Bit
Configuration
Function
Effected
Effect of
Mode Select = 1
During Reset
Effect of
Mode Select = 0
During Reset
EVB
Default
Mode
0 Address Bus Minimum Bus Mode
ADDR[0:11] = CS[0:11]
Maximum Bus Mode
ADDR[0:11] = Address Pins
1
1 Vector Table Location
(IP Bit)
Vector Table
0xFFF0 0000
Vector Table
0x0000 0000
0
2 Burst Type/Indication Type 2/LAST Type 1/BDIP 0
3 Interface Type for
CSBOOT
ITYPE = 001
Asynchronous (Time to
Hi-Z = 2Clk)
ITYPE = 1000
Synchronous Burst
1
4 CSBOOT Port Size 32-Bit 16-Bit 1
5 Reset Configuration
Source For DATA[6:13]
Latch Configuration from
external pins.
Latch Configuration from
internal defaults.
1
[6:8] TA Delay For CSBOOT TA Delay Encoding
000
001
010
011
100
101
110
111
# of Wait States
0
1
2
3
4
5
6
7
100
HARDWARE PREPARATION AND INSTALLATION
MPC505EVBUM/D 2-13
Table 2-7. Data Bus Reset Configuration Word (continued)
Data
Bus
Bit
Configuration
Function
Effected
Effect of
Mode Select = 1
During Reset
Effect of
Mode Select = 0
During Reset
EVB
Default
Mode
[9:10] IMEMBASE[0:1] IMEMBASE
00
01
10
11
Block Placement
Start Addr: 0x0000 0000
End Addr: 0x000F FFFF
Start Addr: 0xFFF0 0000
End Addr: 0xFFFF FFFF
10
[11:12] LMEMBASE[0:1] LMEMBASE
00
01
10
11
SRAM Block Placement
Start address: 0x0000 0000
End address: 0x000F FFFF
Start address: 0xFFF0 0000
End address: 0xFFFF FFFF
11
13 Reset configuration
source for DATA[14:21]
Latch configuration from
external pins
Latch configuration from
internal defaults.
1
14 CT[0:3], AT[0:1], TS CT[0:3], AT[0:1], TS PJ[1:7] 1
15 WR, BDIP WR, BDIP PK[0:1] 0
16 PLLL/DSDO, VF[0:2],
VFLS[0:1], WP[1:5]
DSDO, Pipe Tracking,
Watchpoints
PK[2:7], PL[2:7] 1
17 BURST, TEA, AACK,
TA, BE[0:3]
Handshake Pins PORTI[0:7] 1
18 CR, BI, BR, BB, BG,
ARETRY
Bus Arbitration Pins PM[2:7] 1
19 Release reset when PLL
locked
Release reset when PLL
locked and after 16 clocks
(when not in PLL 1:1
mode)
Hold reset 16 clocks after reset
negated.
1
20 Reserved 0
21 Reset Configuration
Source For DATA[22:31]
Latch Configuration from
external pins.
Latch Configuration from
internal defaults.
1
22 Reserved 0
23 IEN I-bus Memory modules
are enabled.
I-bus Memory modules are
disabled and emulated
externally.
0
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...