Specifications

A Minimal PowerPCª Boot Sequence for 9
Executing Compiled C Programs
Sample Boot Sequence
4.1 ConÞgurable Options
The design of the sample boot sequence allows it to be easily conÞgurable. The many options deÞned in the
header Þles allow the user to choose how the code should execute. These options are summarized in Table 6.
Table 6. User-Configurable Program Options
Option
DeÞnition
Location
DeÞnition Default Value
USER_ENTRY ppcinit.h SpeciÞes the name of the entry point in the user
C program. Corresponds to main() but isnÕt
named main() due to possible compiler
problems.
test_main
ICACHE_ON ppcinit.h SpeciÞes whether to turn on the Instruction
cache.
1 = icache on
0 = icache off
1
DCACHE_ON ppcinit.h SpeciÞes whether to turn on the data cache
1 = dcache on
0 = dcache off
1
L2CACHE_ENABLE ppcinit.h Specify whether to use the L2 cache.
1 = L2 cache on
0 = L2 cache off
This should be set to 0 for processors that donÕt
have an L2 cache, such as 603e
603e: 0
750: 1
7400: 1
L2_INIT ppcinit.h L2CR conÞguration values with the L2E (L2
Enable) bit turned off. SpeciÞes the appropriate
L2 size, clock ratio, RAM type, and hold time.
For the userÕs convenience, #deÞnes of the
various options are provided in the Þle
reg_defs.h. The default is set for a 0.5 MB burst
RAM L2 cache with a clock divisor of 2 and a
hold time of 0.5 nS.
(L2CR_L2SIZ_HM |
L2CR_L2CLK_2 |
L2CR_L2RAM_BU
RST |
L2CR_L2OH_5)
L2_ENABLE ppcinit.h L2CR register value with L2 conÞguration values
set and the L2 cache enabled (L2E set).
(L2_INIT |
L2CR_L2E)
VMX_AVAIL ppcinit.h SpeciÞes whether an AltiVec unit is available on
the processor and that it should be used.
1 = AltiVec unit available
0 = No Altivec unit available, or do not use it
This should be set to 0 for processors without an
AltiVec unit such as 603e and 750.
603e: 0
750: 0
7400: 1
STACK_LOC ppcinit.h 32 bits specifying the stack address for the user
program
0x0007_0000
MMU_ON ppcinit.h SpeciÞes whether or not to use the MMU.
1 = MMU on
0 = MMU off
1
PROM_BASE ppcinit.h The start address of the address range
corresponding to the physical address of the
ROM.
0xFFC0_0000