Specifications

6 A Minimal PowerPCª Boot Sequence for
Executing Compiled C Program s
PowerPC Processor Initialization
When the MMU setup completes, the MMU may be enabled by setting MSR bits 26 and 27, Instruction
Address Translation (IR) and Data Address Translation (DR). At this point, address translation is active.
2.3 Caches
At power-up, the L2 cache (if available) and L1 instruction and data caches are disabled. These should be
turned on to boost program performance. For the MPC603e, MPC750, and MPC7400, turning on the L1
caches requires setting bit 16, instruction cache enable (ICE), and bit 17, data cache enable (DCE) in
hardware implementation register 0 (HID0). An
isync instruction should be issued before setting the ICE
bit to ensure that the cache is not enabled or disabled during an instruction fetch. Similarly, a
sync
instruction should be executed before setting the DCE bit.
The MPC750 and the MPC7400 processors have an L2 cache in addition to the L1 cache. The operation of
this cache is controlled by the L2 cache control register, L2CR. Before enabling the L2 cache, L2CR must
be programmed with the correct L2 size, L2 RAM type, clock ratio, and output hold time, at a minimum. In
addition, the L2 DLL must be allowed to achieve phase lock before the L2 cache is enabled, and the L2 tags
should be invalidated. Both of these tasks can be accomplished by performing a global L2 invalidate, since
the L2 invalidate is guaranteed to take longer than the time required to achieve phase lock. After the L2CR
has been set up, the cache has been invalidated, and the DLL has achieved phase lock, the L2 cache can be
enabled by setting the L2E bit in L2CR.
Caution should be exercised when enabling the caches for certain hardware conÞgurations. If there are
devices on the board that do not support burst reads, then the caches should not be enabled until the MMU
has been set up and enabled to mark these regions as cache-inhibited. Otherwise, the processor will attempt
to burst read from these devices to Þll the cache and possibly cause system errors. For these cases, the caches
should be disabled whenever the MMU is disabled.
Note that simply enabling the caches is not sufÞcient to ensure that the caches will be used if the MMU is
enabled. Memory regions where the user data resides should be mapped as non-cache-inhibited in order to
make use of the cache. See Section 2.2, ÒMemory Management Unit,Ó for more information on mapping
memory regions.
2.4 EABI Register Initialization
In order for user applications to run correctly, registers speciÞed by the Embedded Application Binary
Interface (EABI) must be set up. This is handled by the __eabi() startup code and the code that executes
prior to entry into main(). The sample boot sequence provides a simple __eabi() that initializes registers
GPR2 and GPR13. GPR1 is initialized prior to the call to main() by the init sequence. Part III, ÒPowerPC
EABI Compliance,Ó describes these registers and the other EABI register conventions in more detail.