Specifications

A Minimal PowerPCª Boot Sequence for 5
Executing Compiled C Programs
PowerPC Processor Initialization
In addition, the programmer may specify the memory/cache access modes for the mapped region. These
modes are controlled by the WIMG bits in the lower BAT registers. The WIMG bits are described as follows:
¥ W bitÑSetting the W bit for a memory region causes writes to the region to be written through to
main memory every time a cached copy of the region is modiÞed. If the W bit is set to 0, accesses
are treated as write-back; that is, they are not written into memory until the block is ßushed from
the cache.
¥ I bitÑControls the caching of the region. If the I bit is set to 1, the region becomes cache-inhibited,
and all accesses to the region must take place from main memory. This bit should usually be set for
regions that encompass I/O device memory. Since these devices may dynamically update a memory
location, reading a cached copy can result in accessing old data. Marking the region cache-inhibited
prevents this problem. Memory regions corresponding to devices that do not support burst reads
should also be marked cache-inhibited.
¥ M bitÑSpeciÞes memory coherency. When it is set to 0, the hardware does not enforce data
coherency. Otherwise, accesses to regions with the M bit set cause the hardware to indicate to the
rest of the system that the access occurred. This bit is useful for systems where multiple processors
or other devices can modify the memory. In a minimal single-processor system the M-bit should
usually be set to 0.
¥ G bitÑMarks a memory region as guarded when set to 1. The guarded attribute protects an area of
memory from read accesses that are not directly speciÞed by the program. It is especially useful for
memory regions that have holes. Whenever the processor tries to speculatively load a block of data,
it may attempt to access memory that does not exist. This can cause a machine check exception.
Marking the region as guarded prevents this from occurring. In addition, the guarded attribute can
be used to prevent speculative load operations to device memory, which can cause unpredictable
behavior.
In a complete operating system, MMU setup continues with invalidating TLB entries, initializing the
segment registers, and setting up the page table. Even if only BAT mappings are used for translation, it is
possible that a user program may generate accesses to addresses that are invalid or not mapped by the BAT
registers. In this case, the hardware attempts to look at the page table to resolve the reference. If the page
table pointer and entries have not been initialized, it is possible that they may contain random data and cause
unintended memory accesses. This document does not describe how to perform these actions. Refer to the
PowerPC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors or the
speciÞc reference manual for a particular processor for more information.
Table 4. Block Access Protection Control
Vs Vp PP Block Type
0 0 xx No BAT match
0 1 00 UserÑno access
1 0 00 SupervisorÑno access
0 1 x1 UserÑread only
1 0 x1 SupervisorÑread only
0 1 10 UserÑread/write
1 0 10 SupervisorÑread/write
1 1 00 BothÑno access
1 1 x1 BothÑread only
1 1 10 BothÑread/write