Specifications

30 A Minimal PowerPCª Boot Sequence for
Executing Compiled C Programs
Source Files
* RAM type = burst SRAM
* Output Hold = 0.5ns
*
* These may need to be changed for your board. Refer to your board specs and your
* processor manual for more information on setting up the L2 cache
*/
#define L2_INIT (L2CR_L2SIZ_HM|L2CR_L2CLK_2|L2CR_L2RAM_BURST| L2CR_L2OH_5)
#define L2_ENABLE (L2_INIT | L2CR_L2E)
#endif
/* L1 Instruction and data caches on or off? */
#define ICACHE_ON 1
#define DCACHE_ON 1
/* Where should I put the stack? Upper and lower address bits
This number should be 16-byte aligned (PPC ABI) or 8-byte aligned (PPC EABI)
*/
#define STACK_LOC 0x00070000
/* Do we want to use the MMUÕs address translation ability? */
#define MMU_ON 1
/*
If weÕre using the MMU we need to set up the BAT registers.
Since we donÕt have a nice operating system handling page
table entries and the like for us, the BATs provide the
easiest translation mechanism.
The User must define the bat mappings here. For unused BATs, specify the
BAT as INVALID and having NO_ACCESS as shown for bats 2 and 3 below.
This code maps everything, including the ROM and instruction space as
read-write because weÕre in a simulator and might want to do something
that you wouldnÕt be able to do on real HW. In a real system, ROM and
instruction space is typically mapped Read-only.
The defines used here are found in reg_defs.h.
*/
/*
first, set address ranges for the devices IÕm mapping with the BATs.
The memory model for my board has ROM at fffc00000 and RAM at 0x00000000.
*/
#define PROM_BASE 0xffc00000
#define PRAM_BASE 0x00000000
#define VROM_BASE PROM_BASE
#define VRAM_BASE PRAM_BASE
#define IBAT0L_VAL (PROM_BASE | BAT_CACHE_INHIBITED | BAT_READ_WRITE)
#define IBAT0U_VAL (VROM_BASE|BAT_VALID_SUPERVISOR|BAT_VALID_USER|BAT_BL_4M)