Specifications

A Minimal PowerPCª Boot Sequence for 3
Executing Compiled C Programs
PowerPC Processor Initialization
2.2 Memory Management Unit
A boot program will need to set up the MMU if memory management is required. Using the MMU to
translate memory addresses allows the programmer to specify protections and access controls for individual
regions of memory. For a minimal system with four or fewer memory regions, it is sufÞcient to use block
address translation (BAT) to perform a rudimentary mapping. For more complex systems, the segment
registers and page tables need to be initialized. This document only addresses the minimal conÞguration
using the BAT registers.
The MMU information provided in this document is included for convenience and is not complete. For more
information about using BAT registers and the MMU, refer to the
PowerPC Microprocessor Family: The
Programming Environments for 32-Bit Microprocessors
.
When using the MMU to provide address translation via the BAT registers, each region of memory in the
system should have an associated BAT mapping. These mappings allow the programmer to specify options
such as whether the speciÞed address range is valid for supervisor or user mode, the memory/cache access
mode, and the protection bits for the block. There are eight BAT array entries. Four of these map data regions
(DBATs), while the remaining four entries specify instruction regions (IBATs). Each entry consists of two
registers, one used to specify the upper 32 bits of the BAT entry and the other the lower 32 bits. The different
Þelds of these registers are shown in Table 1 and Table 2.
Table 1. Upper BAT Register Format
Bits Name Description
0Ð14 BEPI Block effective page indexÑCompared with high-order bits of the
logical address to determine if there is a hit in that BAT array entry
15Ð18 Ñ Reserved
19Ð29 BL Block lengthÑEncoding of the length of the block, ranging from 128
Kbytes to 256 Mbytes. See Table 3 for details.
30 Vs Supervisor mode valid bitÑAlong with MSR[PR], speciÞes whether
this block is valid in supervisor mode
31 Vp User mode valid bitÑAlong with MSR[PR], speciÞes whether this block
is valid in user mode.
Table 2. Lower BAT Register Format
Bits Name Description
0Ð14 BRPN Used with the BL Þeld to determine the high-order bits of the physical
address of the block.
15Ð24 Ñ Reserved
25-28 WIMG Memory/cache access mode bits.
W = Write-through
I = Cache inhibited
M = Memory coherence
G = Guarded
The W and G bits should not be written to in the IBAT registers: doing
so produces boundedly undeÞned results.
29 Ñ Reserved
30-31 PP Protection bits for blockÑUsed in combination with Vs and Vp in the
upper BAT to determine the protection for the block. See Table 4 for
details.