Specifications

20 A Minimal PowerPCª Boot Sequence for
Executing Compiled C Programs
Source Files
// hereÕs the real startup code, located outside the exception vector space
system_reset:
addis r0,0,0x0000
// from reset, the BATs are in an unknown state on most PPCs.
// Invalidate them all to avoid error states
mtspr ibat0u,r0
mtspr ibat1u,r0
mtspr ibat2u,r0
mtspr ibat3u,r0
isync
mtspr dbat0u,r0
mtspr dbat1u,r0
mtspr dbat2u,r0
mtspr dbat3u,r0
isync
// If thereÕs L2 cache we enable later, set it up and invalidate it.
// DonÕt turn it on until after the ROM-RAM copy of the image so
// we donÕt preload the caches (in case weÕre going to run a benchmark).
#if L2CACHE_ENABLE == 1
addis r3,r0,L2_INIT@h
ori r3,r3,L2_INIT@l
mtspr l2cr,r3
// This invalidate serves two purposes.
// First, it invalidates the L2 cache.
// Second, it ensures that when this section of code has completed
// execution, the L2 DLL will have stablilzed.
L2_invalidate:
#if defined(MPC7400) && defined(VMX_AVAIL)
.long 0x7e00066c // dssall instruction, not all compilers
// understand it yet. Actually, as
// long as this code is run from hard
// reset, before any data stream touch
// instructions, this instruction isnÕt needed.
// IÕm putting in for correctness in case
// someone cut-and-pastes this code into
// another application.
#endif
sync
oris r3, r3, 0x0020
mtspr l2cr, r3
sync
invalidate:
mfspr r3, l2cr
andi. r3, r3, 0x1
bne invalidate