Specifications

A Minimal PowerPCª Boot Sequence for

Executing Compiled C Program

Overview

Part I Overview

The procedures discussed in this document perform only the minimum amount of work necessary to execute

a user program. The sample boot sequence is designed to run from system reset. It does not contain

exception handling facilities for other exceptions, although the code is located so that it doesnÕt interfere

with exception space. This allows users who wish to provide exception handling to add exception code

without modifying this source. In addition, this code only handles processor setup. It does not initialize any

peripheral devices because it is designed to be run on instruction set simulators, test cards, or small

evaluation boards. No input/output interface is provided. Results are obtained by looking at data saved in

memory via hardware debuggers or simulator commands.

The sample boot sequence uses the PowerPC memory management unit (MMU) to provide basic access

protection for the ROM and RAM regions of memory via block address translation (BAT). The more

advanced features of the MMU, which provide support for paging and segmentation, are not utilized.

The sample boot sequence provided should be linked with a user program to create a ROM image. This

image is then loaded into a ROM device located at the default system reset vector. The sample boot sequence

handles the task of relocating the code and data from ROM to RAM where necessary and then allows the

user program to execute. Upon completion, the boot sequence saves timing information for the user code

and branches to the invalid opcode exception vector.

Part II PowerPC Processor Initialization

This section describes the state of the PowerPC processor at power-up, the MMU, the caches, and the EABI

2.1 General Initialization

At power-up, the PowerPC processor is in a minimal state, with most features, such as caching and address

translation, disabled. External interrupts, the machine check exception, and ßoating-point exceptions are

also disabled. On most systems, the processor starts up in big-endian mode with the exception preÞx set to

0xFFF0_0000. This means that upon system reset (exception vector 0x0100), the processor executes code

beginning at 0xFFF0_0100.

The code located at the system reset vector must handle system initialization. Exception vectors for the

PowerPC are located at increments of 0x0000_0100 from the vector table start address. Since the

initialization code must Þt between the allocated hard reset exception space between 0xFFF0_0100 and

0xFFF0_01FF, it is customary for the reset code to branch to an address beyond the end of the exception

tableÕs allocated space and execute the instruction sequence located there. Addresses starting at

0xFFF0_0100 and ending at 0xFFF0_3000 are reserved for the exception vector table.

A typical initialization sequence performs the necessary processor setup or hardware-speciÞc initialization,

and then enables exceptions. This includes external interrupts, the machine check exception, and ßoating-

point exceptions. In addition, if the vector table is to be relocated once the hardware setup is complete, the

exception preÞx (IP) bit of the machine state register (MSR) must be changed to reßect the new location of

the vector table (0x0000_0100 to 0x0000_3000).