Specifications

18 A Minimal PowerPCª Boot Sequence for
Executing Compiled C Program s
Sample Boot Sequence
4.7 Limitations of the Sample Boot Sequence
The sample boot sequence is intended to be used in a controlled environment and is designed to be as
minimal as possible. As a result, there are some limitations to its design and use as follows:
1. The image should be built to be initially located at either 0xFFF0_0000 or 0x0000_0000.
2. Memory is mapped via the BAT registers. The segment registers and page tables are not used.
3. The segment registers, page table pointer, and page tables are not initialized. Care should be taken
to ensure that programs do not generate references to addresses in ranges not mapped by a BAT
register. Doing so causes the processor to attempt to search the page table (whose location has not
been deÞned and could point anywhere) for a translation. This could possibly result in reading/
writing to random locations in memory.
4. No exception handling code is provided. With the exception of system reset, the exception vector
locations contain the illegal opcode for PowerPC (0x0000_0000).
5. The code only initializes the processor; it does not initialize any peripheral devices and is not
designed to be run in a system with a memory controller such as an MPC106. Additional code must
be added to handle these situations.
6. Programs should avoid making stdio calls such as printf since there is no mechanism for handling
these calls. The standard libraries are not linked with the user code since many of the functions in
these libraries require speciÞc platform support and therefore will not work when there is no OS
running.
7. The sample sequence only performs setup necessary for standard C compiles. C++ programs and
programs written in other languages may require additional support.
8. The sample boot sequence is designed to be minimal and to give the programmer as much control
as possible. It does not use the standard __eabi() provided with the compiler. The standard __eabi()
references symbols are not deÞned by the linking phase of the minimal boot and therefore will not
link correctly.
9. The sample boot sequence has been tested with GNU compiler version 2.8.1 and the gnu linker
version 2.9.1. It is possible and even likely that other versions will work as well.
10. The MPC7400 version of this code was designed to run on a model or chip revision at or greater
than 2.9. Most production processors and models should be at or above this revision level. Previous
chip revisions may require HID0, IABR, MSSCR0, and MSSCR1 to have special settings in order
for some programs to run correctly. This application note does not provide source code to support
these settings.